The most common use of reconfigurable I/O for advanced data acquisition is custom timing and triggering. Below is an example block diagram of a triggered analog input task using NI-DAQmx.
Figure 1. Triggered Analog Input With NI-DAQmx
Instead of using different functions for channel configuration, as shown in Figure 1, this hardware uses functions called FPGA I/O nodes for the reading and writing of all analog and digital channels. Let’s look at the exact same functionality using I/O nodes in LabVIEW FPGA.
Figure 2. Triggered Analog Input With R Series and LabVIEW FPGA
You can see that there are no configuration functions for global channels; sample clocks; triggers; or starting, stopping, and clearing tasks. It’s all been replaced by a simple analog I/O read, and all timing is controlled by native LabVIEW structures such as While Loops and Case structures. Because the entire block diagram executes in FPGA hardware, the LabVIEW code executes with hardware-timed speed and reliability. Let’s look a little deeper into how this block diagram works. Instead of specifying a particular sampling rate, the analog I/O node uses the For Loop to acquire each sample. The corresponding ADC actually digitizes the input signal when the FPGA I/O node is called, and is therefore clocked by the For Loop. If you wanted to sample a signal at 100 kHz, the delay specified for that loop should be set to 10 µs. The loop timer function ensures a specific delay in time, beginning with the second loop iteration, so we’ve used a sequence structure to ensure the specified time period between samples. The Case structure in LabVIEW FPGA is powerful, because it essentially represents a hardware trigger for all the code it encapsulates. With all functions and structures executing in hardware with gates of logic, the Case structure ensures that the sampling begins at the correct moment in time, within 10 µs of accuracy. Lastly, there is no need to clear the task ID or release memory, because we are now working at the hardware level with few layers of abstraction.
The true benefits to using FPGA-based hardware is the ability to customize all timing and triggering, as well as implement signal processing and decision making in hardware. Let’s now see what it takes to modify our analog input trigger for some custom application. What if we wanted to trigger the acquisition if either of two analog input channels exceeded a certain threshold? This is fairly simple to implement in LabVIEW FPGA.
. Custom Triggered Analog Input With R Series and LabVIEW FPGA
You can see that we added a second FPGA I/O node and a second compare function, as well as a Boolean OR function to the block diagram. R Series boards have dedicated ADCs on every analog input channel, so both channels are sampled simultaneously, and if either of those exceeds the specified limit the Case structure executes the true case and begins the acquisition within the same 10 µs of accuracy. Keep in mind that it’s not possible to generate a trigger like this on hardware enabled by NI-DAQmx. You could implement this type of trigger in software, but this would require software-timed decision making with much higher latency. If we wanted to then expand this from monitoring two channels to all eight channels, or even add digital triggers, the customized code wouldn’t be any more complicated. Adding pretrigger scans would involve constantly sampling the input channel and passing data into a first-in-first-out (FIFO) buffer. Once the trigger was read, the FIFO buffer and subsequent samples would then be passed to the host through a DMA channel.
If we wanted to sample a second analog input channel using the NI-DAQmx driver, the block diagram wouldn’t be much different than what is shown in Figure 1. There would still be limitations, however, because both channels would be forced to reference the same trigger and sample at the same clock rate. Let’s look at the different options for sampling multiple channels using reconfigurable I/O and LabVIEW FPGA.
Figure 4. Triggered Simultaneous Analog Input With R Series
Figure 4 (above) shows us how to simultaneously sample from two different analog input channels, based on an analog trigger from analog input channel 0 (AIO). Since all multifunction reconfigurable I/O devices have independent ADCs, two channels within an I/O node are sampled at the exact same instant. Typical multifunction DAQ devices multiplex all channels through a single ADC, and therefore all channels must share the same Sample Clock and trigger lines. Figure 5 (below) shows that multifunction reconfigurable I/O devices can actually sample different analog input channels at independent rates. By placing the analog input I/O nodes within independent loops, each channel can sample at completely different rates, and then stream data independently through two DMA channels.
Figure 5. Triggered Multirate Analog Input With Multifunction Reconfigurable I/O Hardware
Lastly, if we wanted both channels to have independent sampling rates, as well as independent Start Triggers, we could place each I/O node in parallel loop structures as shown in Figure 6. This takes full advantage of FPGA parallelism, where each task uses its own dedicated resources and executes completely independent of any other acquisition task.
Figure 6. Independently Triggered, Multirate Analog Input With Multifunction Reconfigurable I/O Hardware