LabVIEW FPGA 1.1 Embedded Project Manager Known Issues


This document contains the LabVIEW FPGA 1.1 Embedded Project Manager known issues that were discovered before and since the release of the LabVIEW FPGA 1.1 Embedded Project Manager. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

Known Issues

Here is the list of known issues relating to the LabVIEW FPGA Embedded Project Manager. These issues are only relevant to LabVIEW FPGA 1.1 (requires LabVIEW 7.1).

  • Embedded Project Manager Takes a Long Time to Launch
    When the Embedded Project Manager window launches, it searches for FPGA devices. If you have remote systems enabled for remote finding in Measurement & Automation Explorer (MAX) and those systems are not accessible, the Embedded Project Manager window launches slowly due to connection timeouts. Refer to the LabVIEW FPGA Module Release Notes for more information about enabling and disabling remote finding in MAX.
  • Rebind Dialog Prompt After Loading a Project
    This prompt typically appears when there are unbound aliases in the LEP file or when the target changes. However, it may also appear at other times when it is not needed. If this is the case, select the current target from the list or click cancel.
  • Do Not Modify Aliases in the Project While an FPGA VI is Running
    If you modify or delete an alias in the Embedded Project Manager while the VI is running in Interactive or Emulation Mode, the VI may show funny behavior because the VI and the Project will be out of synch.
  • Project With Missing VIs May Not Immediately Prompt You to Find the VIs
    If a Project File is opened by clicking the run button on an open VI and the Project File has references to VIs that cannot be found on disk, you may not be prompted to find the missing VIs until you close the Project File.
  • Deleted Aliases Reappear After Switching to a Different Target
    If you have an FPGA VI that you have used on multiple targets, the Project File will store multiple copies of the Aliases, one set for each target. If you need to permanently delete a specific alias, switch to all targets used, delete the alias, and save the Project file.
  • Adding a VI to the Project Takes Several Minutes
    Depending on the size of the VI, the number of SubVIs, and the number of IO node used on the diagram it may take several seconds to minutes for the Embedded Project Manager to add the VI to the Project. In addition, if the VI needs to be migrated from a previous version, then additional time may be necessary to add the VI to the Project.
  • Specific Project File has Become the Default Project File
    If you double-click a Project file to open LabVIEW, that Project will open by default every time that the Embedded Project Manager is started while LabVIEW is still running. To stop this, restart LabVIEW and open the Project file from the Embedded Project Manager after targeting your FPGA Device.
  • Close Open Project Files Before Building an Application
    If you attempt to build an application from an FPGA VI and a Project file is open containing references to this VI, the LabVIEW Application Builder will be unable to build. Close any open VIs and the Project file before attempting to build an application.
  • Double Clicking a Project File Will Not Load the Project
    If you already have a project open, double-clicking on a Project file in Windows Explorer does nothing. Use the menu item File»Open Project from the Embedded Project Manager to open the Project.
  • Embedded Project Manager Closes when you Target a Real-Time Device
    This is expected since all open VIs are closed when you switch your target to a RT Device. In addition, do not use the Embedded Project Manager while targeted to RT because it will be closed again after switching to a new target from RT.
  • Cancel Button on Embedded Project Manager's Prompt: "Project options have changed.." Does Not Stop the Compile
    This prompt is typically seen when you change the Default FPGA Clock Rate before attempting to compile. Clicking OK will save the Project file and compile at the Default FPGA Clock Rate that you specified. Clicking cancel will keep the previous Default FPGA Clock Rate and still compile. To stop the compile, click cancel on the compiling window that appears.
  • Unable to Remove a VI From the Project
    If a VI is marked as read-only by the operating system, the Embedded Project Manager will be unable to remove the VI from the Project.
  • Previous Bit Files are Out of Date After Switching Targets
    If you have compiled your Project for a particular FPGA device, you will be forced to recompile for that device again if you target and rebind to a different FPGA device. This occurs because the signature of the VI changes and no longer matches the signature on the bitstream generated from the previous device. If you are planning on creating a single FPGA VI for multiple targets, then target each FPGA device you are planning on using, save the VI and the Project, and begin compiling for each target.


Glossary of Terms


  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).