We will start by looking at a single channel from the digital pattern instrument driving to an open connection at the VHDCI connector on the front panel, as shown in Figure 3. An individual digital pattern instrument is calibrated for timing with the front panel as the timing calibration plane. This means that if channels have edges or strobes programmed to occur at the same time, they will be aligned at the front panel.
Note that in an STS, the timing calibration plane is at the POGO interface on the tester. Although the discussion here will generically apply to both cases, the biggest difference for the STS case is that instead of the calibration just needing to adjust for ~700 ps of delay from the pin electronics to the VHDCI connector, it will also need to account for the length of the POGO cable, which can be up to about 5 ns, but may vary depending on the length of the POGO cable.
Internal to the digital pattern instrument, there is a non-zero length trace from the pin electronics chip to the VHDCI connector. This trace is a few inches long and will have an average delay of around 700 ps, but this will vary a little from channel to channel.
When an edge is programmed to be received by the DUT at a particular time, internally the digital pattern instrument needs to launch the edge approximately 700 ps early, non-zero length internal trace, plus the additional flight time from the VHDCI connector to the DUT in order for the edge to make it to the DUT at the right time.
Similarly, for signals coming from the DUT, the sampling of the digital pattern instrument needs to accommodate for the time from the DUT to the VHDCI connector and the time from the VHDCI connector through this internal path before it is seen by the pin electronics. This means that if an edge occurred at time 50 ns at the VHDCI connector, the pin electronics would need to sample it at time ~50.7 ns to correctly show what happened at the front panel at time 50 ns.
Below is an example in the Digital Pattern Editor to show what is happening. This is a basic pattern that will drive a transition on a line at time 50 ns. Figure 4, Figure 5, and Figure 6 show the specification sheet, timing sheet, and the pattern, respectively.
Vector 1 drives a rising edge on pin A at time 50 ns. Since it is return-to-low (RL), the line will go back low at time 75 ns.
Figure 7 shows the Digital Scope after bursting the pattern. In blue (“A” in the image), the Digital Scope shows the ideal waveform with a step from 0 to 1 at time 50 ns. In yellow, we see that the signal sent from the digital pattern instrument is a 1.8 V signal, but since it has a source impedance of ~50 ohms and the transmission line is ~50 ohms, only half of this voltage propagates down the trace immediately (note that since the transmission line is shorter than the edge time, this step is not very pronounced here). When it reaches the high impedance at the end of the transmission line (at the open connection at the front panel), it will reflect, making a full 0 to 1.8 V swing at the front panel at time 50 ns. For sampling, in order to reflect this change to the user, we wait for the flight time for this reflection to get back to the pin electronics—about 700 ps after it was at the front panel. We show this to the user as what happened at the front panel at time 50 ns. You can see this at location “B” in the image, as the reflected signal has the transition up to 1.8 V at time 50 ns.
This becomes slightly more complicated when the initial step occurs at the pin electronics. We know that to drive the edge at the front panel at time 50 ns, the edge needed to be launched ~700 ps early, but it appears that the edge is being launched earlier than this (location “C” in the image). This is because for sampling we always show the signal coming back from the DUT, then adjust it to show the time that occurred at the DUT. In this case, the actual reflected signal got back to the pin electronics at time ~50.7 ns, but this corresponded to that edge at the VHDCI connection at 50 ns, so we display it there on the waveform. However, for the initial step, we needed to launch the edge at time ~49.3 ns to get the edge to the DUT at time 50 ns. Since the comparator timing is compensating to accurately represent the timing of signals at the DUT, this initial step that we drive is seen at 2 x flight time before the edge, happening close to time 48 ns in the image above.