This document contains the NI-RIO 14.5 known issues that were discovered before and since the release of NI-RIO 14.0.1. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered. Each issue appears as a row in the table and includes an issue title, a brief description of the problem, and any workarounds that might help resolve the issue. To help determine if issues have been added since the date of publish, these newly added issues will be in their own section at the top (if applicable).
The workarounds that appear in the document are not always tested by NI and are not guaranteed to resolve the issue. If a workaround refers you to the NI KnowledgeBase, please visit www.ni.com/kb/ and enter that KB number in the search field to locate the specific document. The brief description given does not necessarily describe the problem in full detail, and it is expected that you might want more information on an issue. If you would like more information on an issue feel free to contact NI and referencing the ID number given in the document. You can contact us through any of the normal support channels including phone, email, or the discussion forums. See www.ni.com/contact to contact us. Also consider contacting us if you find a workaround for an issue that is not listed in the document so that we can add the workaround to the document.
cRIO targets supported by Xilinx Vivado Compile Tools experience compilation failures due to timing violation errors when configured for Hybrid Interface mode
When you are using the cRIO-906x and cRIO-903x configured in Hybrid Interface mode and try to compile using Xilinx Vivado Compile Tools 2013.4, the compilation always fails for the following modules: NI 9203, NI 9205, NI 9206, NI 9220, NI 9222, NI 9223, NI 9263, NI 9264, NI 9265, NI 9269. The compilation failure refers to a non-diagram component that is required in the design.
Bitfiles compiled using Xilinx Vivado Compile Tools 14 SP1 may report skipped step or may appear to restart
Several C Series modules might experience an issue in which timing is not being met when using the Xilinx Vivado Compile Tools with LabVIEW 2014 or LabVIEW 2014 SP1. This issue does not affect data integrity or sampling time of the module once compiled.
Using DSA modules in LabVIEW FPGA does not prevent implicit synchronization
You might see error codes 65539 or 65582 when reading channels from two or more Dynamic Signal Acquisition (DSA) modules within the same I/O node. With CompactRIO Module Support 14.0, at the start of compilation a check was performed to ensure DSA modules read within the same I/O node were synchronized with a master clock. This check is disabled.
To avoid this warning or error, place a checkmark in the Export Onboard Clock checkbox in the module properties dialog box in the Project Explorer window. Place a checkmark in the Import Clock checkbox for any slave modules.