Issues recorded after LabVIEW FPGA Module 8.2.1 released
- Digital output not changing when channel is used in a port and a line—A digital line output may stop responding if you use the digital resource as part of a digital port and also a digital line. The problem has to do with arbitration. The new default arbitration of never arbitrate may cause this problem to appear when it previously seemed to work. To fix the problem, change the arbitration setting for the digital line and port to include an arbitor.
- HDL Interface Node : output not handled error— The HDL node now parses the code to ensure the outputs defined on the parameters tab are handled. The parsing algorithm has an issue when spaces are not present in locations it expects. To fix this issue ensure there is a space between all signal names and the parenthesis of subcomponents.
IDSelectEn => Module_DO(4),
IDSelectOut => Module_DO(3),
IDSelectEn => Module_DO (4),
IDSelectOut => Module_DO (3),
Issues recorded after the LabVIEW FPGA Module 8.2 released
- Memory Read function may return incorrect data (Fixed in 8.2.1)—Reading from a Memory Block may return incorrect data for the address specified. This is more likely to occur when accessing the same memory block from many different places.
- FIFO/Memory Blocks emulation may behave incorrectly (Fixed in 8.2.1)—Changing which FIFO/Memory Block a node references does not cause the emulation behavior to change to behave like the new FIFO/Memory Block. Therefore during emulation the node will still behave like the old FIFO/Memory Block. This only effects emulation. The FIFO/Memory Block will take on the newly selected properties when compiled and run in hardware. To workaround this issue only select a FIFO/Memory Block from a node once. If you need to select a different FIFO/Memory Block you should create a new node, or drag the item from the project.
Issues found in the README file
Issues with Importing FPGA Module 1.x Files
- Import utility changes the size of FPGA FIFOs that use block RAM—The import utility causes the FPGA FIFOs using block memory to change size. Right-click the FPGA FIFO in the Project Explorer window and select Properties from the shortcut menu to view the newly configured depth of the FIFO.
- Imported host VI broken—The host VI might import improperly to LabVIEW 8.2 if any of the following conditions apply: 1) you use constants for the HW Exec Ref parameter on the block diagram, 2) you use Call By Reference Nodes that pass the HW Exec Ref parameter, or 3) you use strict type definitions of the HW Exec Ref parameter with property nodes to get or set their value. Open the host VI and manually replace all instances of the HW Exec Ref that are broken with the new HW Exec Ref coming from the Open FPGA VI Reference.
- Imported FPGA VI broken—The FPGA VI might import improperly to LabVIEW 8.2 if any of the following conditions apply: 1) you have multiple aliases pointing to the same resource or 2) you have aliases with the same name that point to different resources. Edit the resources in the Project Explorer window.
- Importing FPGA Module 1.0 VIs broken due to missing flag for Autopreallocate arrays and strings—An FPGA VI created with the FPGA module 1.0 might be broken after importing the VI to LabVIEW 8.2. Make sure that a checkmark appears in the Autopreallocate arrays and strings checkbox. You can find the checkbox by navigating to the Execution category of the VI Properties dialog box for the FPGA VI.
- Import utility replaces Abort method with Reset method—A host VI created with the FPGA module 1.x might have used the Abort method with an Invoke Method function or as part of the Close FPGA VI Reference. The import utility replaces the Abort method with the Reset method. The Abort method in the FPGA Module 1.x reset the FPGA VI to default values. The Reset method in the FPGA Module 8.2 resets the FPGA VI to default values. In the FPGA Module 8.2, the Abort method stops the FPGA VI but does not reset the values to their default values. By replacing the Abort method with the Reset method, the import utility preserves behavior of your program. No action on your part is necessary.
- Disable legacy USB support on PXI Embedded Real-Time controllers—You must disable Legacy USB Support in the BIOS of PXI Embedded Real-Time Controllers when you use the FPGA Interface functions. Specific controllers affected are the PXI-817x controllers and any other third-party systems that use the PhoenixBIOS. Failure to do so can result in the Open FPGA VI Reference function failing to download the FPGA VI without returning an error. Subsequent reads using the Read/Write Control function return values where all bits of the data type are set to 1 without an error. National Instruments also recommends disabling Legacy USB Support when you use the LabVIEW Real-Time Module to reduce jitter. Disable Legacy USB support by configuring the BIOS of the controller. Refer to the Configuring RT Target Settings topic in the LabVIEW Help for information about configuring the BIOS.
- TCP must be installed—Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server. Refer to Knowledge Base 2X6FUU83: My FPGA VI Compilation Fails With An Error Contacting Server, for more information about manually installing TCP support.
- FPGA FIFO reset behavior—When you use an FPGA target emulator, FPGA FIFOs reset when the VI is stopped and then started again. When you use an FPGA target with Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and then started again. To reset the FIFO, right-click the FPGA target in the Project Explorer window and select Reset from the shortcut menu. When you control an FPGA VI using Programmatic FPGA Interface Communication, use the Close FPGA VI Reference function with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs.
- Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server—If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Refer to Knowledge Base 37AEQJVI: Security Alert Dialog Box Appears When Launching LabVIEW on Windows XP SP2 for more information about correcting this problem.
- Slow installation/uninstallation progress—If you click the Modify button in the National Instruments Software dialog box, available in the Add or Remove Programs utility, after you install the LabVIEW FPGA Module, the installer can take up to 10 minutes to initialize without any change in the progress indicator bar.
- Opening host VIs that include the FPGA Interface functions take several minutes to open—Host VIs that contain the FPGA Interface functions might take a long time to open because the FPGA Interface functions need several support files to manage the interface with FPGA VIs. The FPGA Interface functions also verify the status of the FPGA VI when you open the host VI.
- New defaults for compile warning dialog boxes—By default, the FPGA Module no longer shows the Beginning Compile dialog box or Possible Inconsistencies dialog box, which appears when you choose to use a previously compiled FPGA VI bitfile rather than recompile the FPGA VI. Use the FPGA Module Options dialog box to change the default settings. Select Tools»FPGA Module Options to display the FPGA Module Options dialog box.