LabVIEW FPGA IP Builder 2012 Known Issues

Overview

This document contains the LabVIEW FPGA IP Builder 2012 known issues that were discovered before and since the release of LabVIEW FPGA IP Builder 2012. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

The LabVIEW 2012 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.

Document Organization

The Known Issues Document is divided into two separate tables. The following section displays the issues by issue category.

Known Issues by Category

Please refer to Developer Zone Article LabVIEW Known Issues Categories Defined for an explanation of the categories and what types of issues are in each category.

For those who wish to locate the newly reported issues, we have also have published a section of the known issues table sorted by the date the issue was added to the document.

Known Issues by Date

Contacting NI

Feel free to contact NI regarding this document or issues in the document. If you are contacting NI in regards to a specific issue, be sure to reference the ID number given in the document to the NI representative. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting National Instruments). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Visit the NI Website to contact us. Also consider contacting us if you find a workaround for an issue that is not listed in the document so that we can add the workaround to the document.

Known Issues by Category

The following items are known issues in FPGA IP Builder 2012 sorted by Category.

LV FPGA IP Builder
336983 LabVIEW does not return estimation errors despite conflicts between directive settings
315926 FPGA IP Builder does not support Boolean controls with latch mechanical actions
344412 FPGA IP Builder converts some terminals to numeric controls and indicators
356405 Unexpected error might occur if the algorithm VI contains FPGA Module Express VIs
362036 An estimation error occurs if the second-level subVI has unwired array controls
353425 FPGA IP Builder might fail to apply the “Number of pipeline stages” directive



ID Known Issue
LV FPGA IP Builder
336983

Return
LabVIEW does not return estimation errors despite conflicts between directive settings
LabVIEW may not return estimation errors, but may return build errors when you configure directive settings that conflict with each other. For example, if the top-level VI of the algorithm contains an array control and you wire this array directly into a subVI. In the subVI, you access the array elements sequentially. LabVIEW does not return estimation errors if you apply the following directive settings that conflict with each other: * Use the "Element-by-element, unbuffered" option for the array control on the top-level VI interface; * Use the "Complete" partition type for the same array in the subVI.

Workaround: Do not specify conflicting directives. To resolve the build error in this specific example, either change "Element-by-element, unbuffered" to "All elements" or disable partitioning for this array.

Reported Version: EAR    Resolved Version: N/A    Added: 03/05/2012
315926

Return
FPGA IP Builder does not support Boolean controls with latch mechanical actions
FPGA IP Builder does not implement the latch mechanical actions on Boolean controls. All Boolean controls in the FPGA IP Builder context are treated as controls with switching mechanical actions.

Workaround: Modify the Boolean controls to use the switching mechanical action.

Reported Version: EAR    Resolved Version: N/A    Added: 07/11/2012
344412

Return
FPGA IP Builder converts some terminals to numeric controls and indicators
If the top-level algorithm VI contains front panel controls/indicators such as rings, graphs, or lists, the FPGA IP Builder converts them into numeric controls or indicators when generating the FPGA IP.

Workaround: Before using the FPGA IP, open the front panel and replace the numeric controls or indicators with the original controls or indicators on the front panel of the algorithm VI.

Reported Version: EAR    Resolved Version: N/A    Added: 07/11/2012
356405

Return
Unexpected error might occur if the algorithm VI contains FPGA Module Express VIs
If the algorithm VI contains any of the following FPGA Module Express VIs, you still can create a directives item for this VI. You also can create build specifications for this directives item. However, an unexpected error might occur when you double-click this directives item or generate FPGA IP from the build specifications: * Sine Wave Generator * Square Wave Generator * White Noise Generator * Quantizer * Basic Discrete Delay * Look-Up Table 1D

Workaround: When you create algorithm VIs, avoid using the FPGA Module Express VIs listed above.

Reported Version: EAR    Resolved Version: N/A    Added: 07/11/2012
362036

Return
An estimation error occurs if the second-level subVI has unwired array controls
Suppose A.vi is a subVI of the top-level algorithm VI, B.vi is a subVI of A.vi, and B.vi contains some array controls and array indicators. On the block diagram of A.vi, if any array control of B.vi is not wired but the corresponding array indicator is wired, you might encounter an error when estimating the directive settings. The error might look similar to the following message: “declaration of xxxx shadows a parameter”.

Workaround: Wire the array control by right-clicking the corresponding terminal and selecting Create>>Constant from the shortcut menu.

Reported Version: EAR    Resolved Version: N/A    Added: 07/11/2012
353425

Return
FPGA IP Builder might fail to apply the “Number of pipeline stages” directive
If you apply the “Number of pipeline stages” directive to a Multiply function that requires two DSP48s, the FPGA IP Builder might fail to apply this directive and returns a warning in the log of the estimation report. The following is an example warning message that the FPGA IP Builder might return: "@W [SYN-303] Cannot apply functional unit assignment of 'PipeMult2S' (f_0.cpp:44) on 'partselect' operation ('__Result__', f_0.cpp:42) due to incompatible operation sets."

Workaround: N/A.

Reported Version: 2012    Resolved Version: N/A    Added: 12/14/2012

Known Issues by Date

The following items are known issues in FPGA IP Builder 2012 sorted by Date.

336983 LabVIEW does not return estimation errors despite conflicts between directive settings
315926 FPGA IP Builder does not support Boolean controls with latch mechanical actions
344412 FPGA IP Builder converts some terminals to numeric controls and indicators
356405 Unexpected error might occur if the algorithm VI contains FPGA Module Express VIs
362036 An estimation error occurs if the second-level subVI has unwired array controls
353425 FPGA IP Builder might fail to apply the “Number of pipeline stages” directive



ID Known Issue
336983

Return
LabVIEW does not return estimation errors despite conflicts between directive settings
LabVIEW may not return estimation errors, but may return build errors when you configure directive settings that conflict with each other. For example, if the top-level VI of the algorithm contains an array control and you wire this array directly into a subVI. In the subVI, you access the array elements sequentially. LabVIEW does not return estimation errors if you apply the following directive settings that conflict with each other: * Use the "Element-by-element, unbuffered" option for the array control on the top-level VI interface; * Use the "Complete" partition type for the same array in the subVI.

Workaround: Do not specify conflicting directives. To resolve the build error in this specific example, either change "Element-by-element, unbuffered" to "All elements" or disable partitioning for this array.

Reported Version: EAR    Resolved Version: N/A    Added: 03/05/2012
315926

Return
FPGA IP Builder does not support Boolean controls with latch mechanical actions
FPGA IP Builder does not implement the latch mechanical actions on Boolean controls. All Boolean controls in the FPGA IP Builder context are treated as controls with switching mechanical actions.

Workaround: Modify the Boolean controls to use the switching mechanical action.

Reported Version: EAR    Resolved Version: N/A    Added: 07/11/2012
344412

Return
FPGA IP Builder converts some terminals to numeric controls and indicators
If the top-level algorithm VI contains front panel controls/indicators such as rings, graphs, or lists, the FPGA IP Builder converts them into numeric controls or indicators when generating the FPGA IP.

Workaround: Before using the FPGA IP, open the front panel and replace the numeric controls or indicators with the original controls or indicators on the front panel of the algorithm VI.

Reported Version: EAR    Resolved Version: N/A    Added: 07/11/2012
356405

Return
Unexpected error might occur if the algorithm VI contains FPGA Module Express VIs
If the algorithm VI contains any of the following FPGA Module Express VIs, you still can create a directives item for this VI. You also can create build specifications for this directives item. However, an unexpected error might occur when you double-click this directives item or generate FPGA IP from the build specifications: * Sine Wave Generator * Square Wave Generator * White Noise Generator * Quantizer * Basic Discrete Delay * Look-Up Table 1D

Workaround: When you create algorithm VIs, avoid using the FPGA Module Express VIs listed above.

Reported Version: EAR    Resolved Version: N/A    Added: 07/11/2012
362036

Return
An estimation error occurs if the second-level subVI has unwired array controls
Suppose A.vi is a subVI of the top-level algorithm VI, B.vi is a subVI of A.vi, and B.vi contains some array controls and array indicators. On the block diagram of A.vi, if any array control of B.vi is not wired but the corresponding array indicator is wired, you might encounter an error when estimating the directive settings. The error might look similar to the following message: “declaration of xxxx shadows a parameter”.

Workaround: Wire the array control by right-clicking the corresponding terminal and selecting Create>>Constant from the shortcut menu.

Reported Version: EAR    Resolved Version: N/A    Added: 07/11/2012
353425

Return
FPGA IP Builder might fail to apply the “Number of pipeline stages” directive
If you apply the “Number of pipeline stages” directive to a Multiply function that requires two DSP48s, the FPGA IP Builder might fail to apply this directive and returns a warning in the log of the estimation report. The following is an example warning message that the FPGA IP Builder might return: "@W [SYN-303] Cannot apply functional unit assignment of 'PipeMult2S' (f_0.cpp:44) on 'partselect' operation ('__Result__', f_0.cpp:42) due to incompatible operation sets."

Workaround: N/A.

Reported Version: 2012    Resolved Version: N/A    Added: 12/14/2012

Document last updated on 12/14/2012

Glossary of Terms

 

  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com.  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).