Archived: LabVIEW 2013 FPGA Module Known Issues

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This document contains the LabVIEW 2013 FPGA Module known issues that were discovered before and since the release of LabVIEW 2013 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

The LabVIEW 2013 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.

Known Issues by Category

The following items are known issues in LabVIEW 2013 SP1 FPGA Module sorted by Category.

Building and Distributing LabVIEW Applications
98807 Host VI does not get notified of changes when building an application
247993 Removing a C-Series Module in a Project Forces Recompilation
410716 The host computer may think the LabVIEW FPGA VI needs to be compiled erroneously
Compatibility
412610 The LabVIEW FPGA Linux Compile Worker hangs during configuration on RHEL 5.6 x64 (Japanese)
413605 FIFO Depth may be coerced to a value lower than specified without alerting the user
401659 Having mismatched versions of the LabVIEW FPGA Compile Server and Client produces a confusing error message
Controls and Indicators
401588 Controls/Indicators with Unsupported Data Types Inside a Diagram Disable Structure Causes Internal Compilation Error
420143 Type def FPGA refnum controls with a label containing carriage returns breaks refnum wire
Documentation
409860 The LabVIEW FPGA Module Release and Upgrade Notes incorrectly claim that Xilinx does not officially support Windows 7
External Code
238241 When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.
303501 Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration.
Functions, VIs, and Express VIs
313940 The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values
357204 Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
380249 Converting the "Look-up Table 1D" Express VI to a sub-VI may cause LabVIEW to hang during compilation
352262 "In Range and Coerce" behavior mismatch between host and FPGA execution for FXP types
411550 The In Range and Coerce function may return an incorrect result for some Fixed-Point configurations
412467 Execution on the Desktop Computer will fail for Dynamic Dispatch VIs containing Handshake Nodes
413443 The IP Integration Node configuration window may hang
414753 The Desktop Execution Node may throw error 1193 when attempting to connect to a running FPGA VI
393669 Switching the order of the Input Terminals on the SCTL causes a compile error.
401546 Memory Item Simulation may not match in hardware behavior
403661 Changing the label of a Control or Indicator on your LabVIEW FPGA VI may cause the Desktop Execution Node to throw an error.
404665 The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set
434094 Using a homogenous cluster as the x input to an "In Range and Coerce" primitive may cause compilation errors.
LabVIEW Project
425132 Installation of LabVIEW FPGA 2013 and NI-RIO 13.0 breaks the FPGA project wizard in earlier versions of LabVIEW FPGA installed on the same computer
Miscellaneous
197816 Virtex 6 design with PLLs simulation run forever
403070 The LabVIEW FPGA Compile Worker may fail to shutdown properly
409261 The Waveform Sampling Probe Window transition buttons may not behave as expected on 1st press
409275 QuestaSim may crash unexpectedly
410377 Simulating a FPGA VI that contains IP Integration Nodes may lock up LabVIEW
364903 Xilinx Coregen Nodes may fail configuration on slow PCs
367915 Removal of Implicit Enable Signals in SCTL causes unexpected DMA FIFO reset behavior
382051 Arithmetic on an Array of Clusters containing an Array of Numerics fails to compile inside an SCTL
381497 Local variable read connected to indicator of subVI in Single Cycle Timed Loop behaves different in simulation than in hardware
Performance
389331 All Spartan6 Block RAM instantiations use a 36bit data width
Upgrade - Behavior Change
401588 Controls/Indicators with Unsupported Data Types Inside a Diagram Disable Structure Causes Internal Compilation Error
Upgrade - Migration
392441 Statically referenced FPGA VIs must be reconfigured if upgraded to LabVIEW 2013



ID Known Issue
Building and Distributing LabVIEW Applications
98807

Return
Host VI does not get notified of changes when building an application
If you make changes to an FPGA VI without saving the host VI, the host VI refers to the old FPGA VI when you build an application.

Workaround: You must open and save the host VI before building an application.

Reported Version: 8.5    Resolved Version: N/A    Added: 08/04/2009
247993

Return
Removing a C-Series Module in a Project Forces Recompilation
Removing a module from a Chassis in a LabVIEW FPGA Project will force a recompilation, even if all VIs in the Build Specification's hierarchy do not reference the module.

Workaround: NA

Reported Version: 2010    Resolved Version: N/A    Added: 07/11/2012
410716

Return
The host computer may think the LabVIEW FPGA VI needs to be compiled erroneously
If a LabVIEW FPGA VI uses Object Oriented Programming, then LabVIEW will notify you that the FPGA VI needs to be compiled (erroneously) when the host is run.

Workaround: Open the LabVIEW FPGA VI before running the host. Having the FPGA VI open when running the host prevents this error.

Reported Version: 2013    Resolved Version: 2014    Added: 07/19/2013
Compatibility
412610

Return
The LabVIEW FPGA Linux Compile Worker hangs during configuration on RHEL 5.6 x64 (Japanese)
When configuring the server for the LabVIEW FPGA Linux Compile Worker on a Japanese version of RHEL, the utility may hang when the configure button is pressed.

Workaround: Install an English version of Linux Red Hat EP 5.6 64bit. An additional unconfirmed workaround is to set the keyboard settings to QWERTY.

Reported Version: 2012    Resolved Version: N/A    Added: 07/17/2013
413605

Return
FIFO Depth may be coerced to a value lower than specified without alerting the user
If a FIFO is created on a target that allows very large FIFO depths, and is then moved to a target whose FPGA only supports smaller FIFOs, the LabVIEW FPGA Module will coerce the FIFO size to an appropriate size for the new target. Depending on the target, the user may not be notified of the change.

Workaround: N/A

Reported Version: 2013    Resolved Version: 2014    Added: 07/17/2013
401659

Return
Having mismatched versions of the LabVIEW FPGA Compile Server and Client produces a confusing error message
If the 2012 version of the Compile Server is installed, and attempts to compile to a 2013 Client, the user will receive the following error: An error occurred attempting to connect to this compile server. Details: NI-Farm: Cannot communicate with the NI-Farm server using the specified communication protocol.

Workaround: Install the 2013 version of the NI Compile Server.

Reported Version: 2012    Resolved Version: N/A    Added: 07/19/2013
Controls and Indicators
401588

Return
Controls/Indicators with Unsupported Data Types Inside a Diagram Disable Structure Causes Internal Compilation Error
A control or indicator with an unsupported data type (e.g., Double) inside the disabled case of a diagram disable structure (or conditional disable structure) will cause an internal error at compile time.

Workaround: Remove all controls or indicators with unsupported data types from the block diagram.

Reported Version: 2012    Resolved Version: 2014    Added: 04/05/2013
420143

Return
Type def FPGA refnum controls with a label containing carriage returns breaks refnum wire
In an FPGA host application, a type defined FPGA refnum control with a carriage return in it's label will break the refnum wire on the block diagram.

Workaround: Don't use carriage returns in the label for FPGA refnum controls.

Reported Version: 2013    Resolved Version: 2014    Added: 11/11/2013
Documentation
409860

Return
The LabVIEW FPGA Module Release and Upgrade Notes incorrectly claim that Xilinx does not officially support Windows 7
According to Xilinx, Windows 7 is a supported OS for the ISE toolchain, which is included with the LabVIEW FPGA Module. For more information on Xilinx ISE OS support, please see http://www.xilinx.com/ise/ossupport/index.htm.

Workaround: N/A

Reported Version: 2013    Resolved Version: N/A    Added: 07/17/2013
External Code
238241

Return
When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.
When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.

Workaround: The wizard only extracts information from the top-level VHDL file, so add another VHDL wrapper that instantiates the original wrapper. In the new wrapper, do not mention the entity attribute.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
303501

Return
Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration.
When you use IP Integration Node to wrap your IP and the top-level VHDL has constants or types in the generic and/or port declaration which are defined in your package files, a Xilinx error will be reported saying that the string constants are not declared when you compile.

Workaround: Add full namespace to the string constants in the generic and/or port declaration of the top-level VHDL.

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
Functions, VIs, and Express VIs
313940

Return
The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values
Due to a roundoff error that may occur with small variance values relative to the mean, the Mean,Variance, and Standard Deviation Express VI may return incorrect results for signals with a substantial DC offset.

Workaround: Edit the SubVI to adapt it to a configuration that meets your application's specific needs. For more information, please see the following forum thread: http://forums.ni.com/t5/LabVIEW/labview-2010-FPGA-problem-with-mean-variance-subvi/td-p/1659110

Reported Version: 2011    Resolved Version: N/A    Added: 07/10/2012
357204

Return
Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
The Compound Arithmetic function may execute operations in a different order on the FPGA than on the desktop, producing slightly different results for floating-point operations. The differences include small rounding discrepancies as well as NaN and Inf behavior.

Workaround: Decompose the Compound Arithmetic Function into individual arithmetic functions to force the order of operations to conform to what you expect.

Reported Version: 2012 32-bit    Resolved Version: N/A    Added: 07/10/2012
380249

Return
Converting the "Look-up Table 1D" Express VI to a sub-VI may cause LabVIEW to hang during compilation
Converting the "Look-up Table 1D" Express VI to a sub-VI generates invalid LabVIEW FPGA code, that causes a crash or hang during the generation of intermediate files.

Workaround: Use the Express VI without converting it to a sub-VI

Reported Version: 2012    Resolved Version: N/A    Added: 12/12/2012
352262

Return
"In Range and Coerce" behavior mismatch between host and FPGA execution for FXP types
The "In Range?" output behavior or the "In Range and Coerce" function doesn't match the desktop for cases where FXP inputs are rounded to the 64-bit word length limit (due to non-aligned or disjoint input types). LabVIEW FPGA rounds the inputs to the output type before doing the comparisons, whereas the desktop does a true numeric comparison before coercing to the output type.

Workaround: Use coerce inputs to the same type before passing them to the "In Range and Coerce" function to force the same behavior.

Reported Version: 2011    Resolved Version: N/A    Added: 12/14/2012
411550

Return
The In Range and Coerce function may return an incorrect result for some Fixed-Point configurations
When using Fixed-Point numbers with extremely large deltas (e.g., Word Length: 1, Integer Word Length 900) the In Range and Coerce function may return an invalid value. Typically, In Range will return a True value incorrectly.

Workaround: Use the TypeCast function to convert the FXP number to an Integer before using the In Range and Coerce function for FXP configurations with very large deltas.

Reported Version: 2012    Resolved Version: N/A    Added: 07/17/2013
412467

Return
Execution on the Desktop Computer will fail for Dynamic Dispatch VIs containing Handshake Nodes
Attempting to Simulate a project with a Handshake Node inside a Dynamic Dispatch VI will fail with the following error: "The handshake is outside a single-cycle Timed Loop. Handshake items are supported only inside a single-cycle Timed Loop."

Workaround: Use a conditional disable structure to use two Register primitives instead of Handshake Nodes during simulation

Reported Version: 2013    Resolved Version: 2014    Added: 07/17/2013
413443

Return
The IP Integration Node configuration window may hang
If the IP Integration node references a file whose path on disk is longer than 140 characters will hang an underlying dependency of the IP Integration Node.

Workaround: Restrict the file path length of any files referenced by the IP Integration node to 140 characters

Reported Version: 2012    Resolved Version: N/A    Added: 07/17/2013
414753

Return
The Desktop Execution Node may throw error 1193 when attempting to connect to a running FPGA VI
If the Desktop Execution Node is used to access a Boolean Control whose mechanical action is set to Latch, the configuration dialog will throw error 1193.

Workaround: Stop execution of the FPGA VI before configuring the Desktop Execution Node.

Reported Version: 2013    Resolved Version: 2014    Added: 07/17/2013
393669

Return
Switching the order of the Input Terminals on the SCTL causes a compile error.
Changing the order of the Input Clock and Error Input terminals on the Single Cycle Timed Loop will result in a compile error.

Workaround: Leave the Input Clock terminal as the first input.

Reported Version: 2012    Resolved Version: 2014    Added: 07/19/2013
401546

Return
Memory Item Simulation may not match in hardware behavior
It is possible to successfully simulate a memory item set to "Never Arbitrate" and then accessed simultaneously by two different Read Methods. This will not work in hardware, and may cause compilation failures

Workaround: N/A

Reported Version: 2012    Resolved Version: N/A    Added: 07/19/2013
403661

Return
Changing the label of a Control or Indicator on your LabVIEW FPGA VI may cause the Desktop Execution Node to throw an error.
If you change the label of a control or indicator on the Front Panel of your FPGA VI that is part of a Desktop Execution Node's configuration, then the Desktop Execution Node will report that the data type of the resource has changed the next time it is run.

Workaround: Open the Desktop Execution Node configuration window, and press the OK button.

Reported Version: 2013    Resolved Version: 2014    Added: 07/19/2013
404665

Return
The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set
According to the LabVIEW FPGA help documentation, the FIFO.configure method will clear the contents of the host-side FIFO buffer. This is not true if the FIFO.configure method does not change the "Actual Depth" of the host-side FIFO.

Workaround: Use FIFO.Stop and FIFO.Start to clear the host-side FIFO buffer.

Reported Version: 2012 SP1    Resolved Version: N/A    Added: 07/19/2013
434094

Return
Using a homogenous cluster as the x input to an "In Range and Coerce" primitive may cause compilation errors.
When a homogeneous cluster is used as the x input to an "In Range and Coerce" primitive and the "Coerced(x)" output is not wired to anything, HDL errors may occur during compilation.

Workaround: Wire an indicator to the "Coerced(x)" output of the primitive.

Reported Version: 2013    Resolved Version: N/A    Added: 11/11/2013
LabVIEW Project
425132

Return
Installation of LabVIEW FPGA 2013 and NI-RIO 13.0 breaks the FPGA project wizard in earlier versions of LabVIEW FPGA installed on the same computer
If you have a versions of LabVIEW FPGA installed that is 2012 SP1 or earlier and then install LabVIEW FPGA 2013 and NI-RIO 13.0, the FPGA project wizard may be broken in the earlier versions of LabVIEW.

Workaround: If the wizard is needed for both versions, isolate the installations from one another on separate drives or on separate machines (real or virtual).

Reported Version: 2012 SP1    Resolved Version: N/A    Added: 11/11/2013
Miscellaneous
197816

Return
Virtex 6 design with PLLs simulation run forever
Currently there is not a mechanism to stop the Virtex 6 PLL from running, which can cause the simulation to continue running when the "Run All" command is used in the simulator.

Workaround: You can use one of the following options to stop the simulation: * Add an assertion failure to the of end your test bench. * Run the test bench for a specified amount of time.

Reported Version: 2010    Resolved Version: N/A    Added: 07/11/2012
403070

Return
The LabVIEW FPGA Compile Worker may fail to shutdown properly
If a Xilinx process hangs during compilation, then the FPGA Compile worker may fail to shutdown properly.

Workaround: Manually kill the hung Xilinx process

Reported Version: 2012    Resolved Version: N/A    Added: 07/19/2013
409261

Return
The Waveform Sampling Probe Window transition buttons may not behave as expected on 1st press
If the vertical yellow line is not already displayed on the graph, then the first press of the transition buttons in the Waveform Sampling Probe window will appear to do nothing.

Workaround: Click on the graph before using the buttons, or press the button twice.

Reported Version: 2013    Resolved Version: 2014    Added: 07/19/2013
409275

Return
QuestaSim may crash unexpectedly
Certain designs may cause QuestaSim to crash, even with designs that correctly simulate in ISIM.

Workaround: Upgrade to QuestaSim 10.0d or 10.2b

Reported Version: 2013    Resolved Version: 2014    Added: 07/19/2013
410377

Return
Simulating a FPGA VI that contains IP Integration Nodes may lock up LabVIEW
Simulating a FPGA VI (in both My Computer and FPGA Contexts) that contains IP Integration Nodes may cause a dialog that states that Xilinx is out of memory or LabVIEW may lock up. This only occurs if users start and stop the VI multiple times or has a Host VI that opens, runs, and closes the VI multiple times. Cause: Memory leaks in third-party tools cause the IP Integration Node to leak memory during its initialization routines. Running this initialization routine multiple times can cause the system to run out of memory causing the third party tools to error out or crash, resulting in LabVIEW becoming unresponsive.

Workaround: Avoid simulating multiple IP Integration Nodes and/or avoid simulating your FPGA VI multiple times in the same instance of LabVIEW. Shutdown LabVIEW to allow the third party tools to release the leaked memory.

Reported Version: 2013    Resolved Version: N/A    Added: 07/19/2013
364903

Return
Xilinx Coregen Nodes may fail configuration on slow PCs
Xilinx Coregen configuration may return the following error on slow PCs: Error 7 occurred at Open/Create/Replace File in MD5Checksum File.vi->niFpgaXIPINIsFuse2Needed.vi->niFpgaXIPINConfPage1.vi Possible reason(s): LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.

Workaround: N/A

Reported Version: 2012    Resolved Version: N/A    Added: 07/22/2013
367915

Return
Removal of Implicit Enable Signals in SCTL causes unexpected DMA FIFO reset behavior
When a Single Cycle Timed Loop enables the Removal of Implicit Enable Signals, the VIs clocking behavior changes so that the VI's clock does not run until the VI is run. Any DMA FIFOs within this SCTL will have the portion of the FIFO inside this clock domain reset immediately when the clock begins. While the FIFO is resetting (approximately 2 clock cycles), any data written to the DMA FIFO from this time domain will be lost.

Workaround: N/A

Reported Version: 2012    Resolved Version: 2014    Added: 07/22/2013
382051

Return
Arithmetic on an Array of Clusters containing an Array of Numerics fails to compile inside an SCTL
Performing an arithmetic operation (e.g. addition) in a Single Cycle Timed Loop on a fixed size array containing a cluster that contains a fixed size array of Numerics incorrectly produces a code-gen error stating that the arithmetic operation cannot be performed in a Single Cycle.

Workaround: Index, un-bundle, and index the desired value before passing it into the arithmetic function.

Reported Version: 2012 SP1    Resolved Version: 2014    Added: 07/22/2013
381497

Return
Local variable read connected to indicator of subVI in Single Cycle Timed Loop behaves different in simulation than in hardware
In the FPGA context, a subVI in a single cycle timed loop which contains an indicator that returns a read from a local variable behaves differently in simulation than in hardware execution. The data from the local variable read should be delayed one cycle to be in accordance with how it behaves in hardware.

Workaround: Enforce data flow by ordering the local variable write followed by the local variable read connected to the indicator.

Reported Version: 2012    Resolved Version: 2014    Added: 11/11/2013
Performance
389331

Return
All Spartan6 Block RAM instantiations use a 36bit data width
When using the Block RAM in a Spartan6 FPGA target, all data types will consume 36 bits of RAM (72 bits for 64bit data types).

Workaround: For smaller data types, use the Join primitives to pack numbers into 32bit wide chunks to ensure more efficient Block RAM utilization. When reading the data back, use the Split primitive, or the Number to Boolean Array and Array Index functions to access the desired element.

Reported Version: 2011    Resolved Version: N/A    Added: 07/17/2013
Upgrade - Behavior Change
401588

Return
Controls/Indicators with Unsupported Data Types Inside a Diagram Disable Structure Causes Internal Compilation Error
A control or indicator with an unsupported data type (e.g., Double) inside the disabled case of a diagram disable structure (or conditional disable structure) will cause an internal error at compile time.

Workaround: Remove all controls or indicators with unsupported data types from the block diagram.

Reported Version: 2012    Resolved Version: 2014    Added: 04/05/2013
Upgrade - Migration
392441

Return
Statically referenced FPGA VIs must be reconfigured if upgraded to LabVIEW 2013
If a statically referenced FPGA VI is used in the host VI, and then upgraded to LabVIEW 2013, Error -52005, Invalid Parameter, will be thrown.

Workaround: Reconfigure the Open Fpga VI Reference and reset the path to the bitfile.

Reported Version: 2013    Resolved Version: N/A    Added: 07/19/2013

Known Issues by Date

The following items are known issues in LabVIEW 2013 SP1 FPGA Module sorted by Date.

98807 Host VI does not get notified of changes when building an application
238241 When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.
303501 Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration.
313940 The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values
357204 Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
197816 Virtex 6 design with PLLs simulation run forever
247993 Removing a C-Series Module in a Project Forces Recompilation
380249 Converting the "Look-up Table 1D" Express VI to a sub-VI may cause LabVIEW to hang during compilation
352262 "In Range and Coerce" behavior mismatch between host and FPGA execution for FXP types
401588 Controls/Indicators with Unsupported Data Types Inside a Diagram Disable Structure Causes Internal Compilation Error
389331 All Spartan6 Block RAM instantiations use a 36bit data width
409860 The LabVIEW FPGA Module Release and Upgrade Notes incorrectly claim that Xilinx does not officially support Windows 7
411550 The In Range and Coerce function may return an incorrect result for some Fixed-Point configurations
412467 Execution on the Desktop Computer will fail for Dynamic Dispatch VIs containing Handshake Nodes
412610 The LabVIEW FPGA Linux Compile Worker hangs during configuration on RHEL 5.6 x64 (Japanese)
413443 The IP Integration Node configuration window may hang
413605 FIFO Depth may be coerced to a value lower than specified without alerting the user
414753 The Desktop Execution Node may throw error 1193 when attempting to connect to a running FPGA VI
392441 Statically referenced FPGA VIs must be reconfigured if upgraded to LabVIEW 2013
393669 Switching the order of the Input Terminals on the SCTL causes a compile error.
401546 Memory Item Simulation may not match in hardware behavior
401659 Having mismatched versions of the LabVIEW FPGA Compile Server and Client produces a confusing error message
403070 The LabVIEW FPGA Compile Worker may fail to shutdown properly
403661 Changing the label of a Control or Indicator on your LabVIEW FPGA VI may cause the Desktop Execution Node to throw an error.
404665 The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set
409261 The Waveform Sampling Probe Window transition buttons may not behave as expected on 1st press
409275 QuestaSim may crash unexpectedly
410377 Simulating a FPGA VI that contains IP Integration Nodes may lock up LabVIEW
410716 The host computer may think the LabVIEW FPGA VI needs to be compiled erroneously
364903 Xilinx Coregen Nodes may fail configuration on slow PCs
367915 Removal of Implicit Enable Signals in SCTL causes unexpected DMA FIFO reset behavior
382051 Arithmetic on an Array of Clusters containing an Array of Numerics fails to compile inside an SCTL
381497 Local variable read connected to indicator of subVI in Single Cycle Timed Loop behaves different in simulation than in hardware
420143 Type def FPGA refnum controls with a label containing carriage returns breaks refnum wire
425132 Installation of LabVIEW FPGA 2013 and NI-RIO 13.0 breaks the FPGA project wizard in earlier versions of LabVIEW FPGA installed on the same computer
434094 Using a homogenous cluster as the x input to an "In Range and Coerce" primitive may cause compilation errors.



ID Known Issue
98807

Return
Host VI does not get notified of changes when building an application
If you make changes to an FPGA VI without saving the host VI, the host VI refers to the old FPGA VI when you build an application.

Workaround: You must open and save the host VI before building an application.

Reported Version: 8.5    Resolved Version: N/A    Added: 08/04/2009
238241

Return
When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.
When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.

Workaround: The wizard only extracts information from the top-level VHDL file, so add another VHDL wrapper that instantiates the original wrapper. In the new wrapper, do not mention the entity attribute.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
303501

Return
Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration.
When you use IP Integration Node to wrap your IP and the top-level VHDL has constants or types in the generic and/or port declaration which are defined in your package files, a Xilinx error will be reported saying that the string constants are not declared when you compile.

Workaround: Add full namespace to the string constants in the generic and/or port declaration of the top-level VHDL.

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
313940

Return
The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values
Due to a roundoff error that may occur with small variance values relative to the mean, the Mean,Variance, and Standard Deviation Express VI may return incorrect results for signals with a substantial DC offset.

Workaround: Edit the SubVI to adapt it to a configuration that meets your application's specific needs. For more information, please see the following forum thread: http://forums.ni.com/t5/LabVIEW/labview-2010-FPGA-problem-with-mean-variance-subvi/td-p/1659110

Reported Version: 2011    Resolved Version: N/A    Added: 07/10/2012
357204

Return
Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
The Compound Arithmetic function may execute operations in a different order on the FPGA than on the desktop, producing slightly different results for floating-point operations. The differences include small rounding discrepancies as well as NaN and Inf behavior.

Workaround: Decompose the Compound Arithmetic Function into individual arithmetic functions to force the order of operations to conform to what you expect.

Reported Version: 2012 32-bit    Resolved Version: N/A    Added: 07/10/2012
197816

Return
Virtex 6 design with PLLs simulation run forever
Currently there is not a mechanism to stop the Virtex 6 PLL from running, which can cause the simulation to continue running when the "Run All" command is used in the simulator.

Workaround: You can use one of the following options to stop the simulation: * Add an assertion failure to the of end your test bench. * Run the test bench for a specified amount of time.

Reported Version: 2010    Resolved Version: N/A    Added: 07/11/2012
247993

Return
Removing a C-Series Module in a Project Forces Recompilation
Removing a module from a Chassis in a LabVIEW FPGA Project will force a recompilation, even if all VIs in the Build Specification's hierarchy do not reference the module.

Workaround: NA

Reported Version: 2010    Resolved Version: N/A    Added: 07/11/2012
380249

Return
Converting the "Look-up Table 1D" Express VI to a sub-VI may cause LabVIEW to hang during compilation
Converting the "Look-up Table 1D" Express VI to a sub-VI generates invalid LabVIEW FPGA code, that causes a crash or hang during the generation of intermediate files.

Workaround: Use the Express VI without converting it to a sub-VI

Reported Version: 2012    Resolved Version: N/A    Added: 12/12/2012
352262

Return
"In Range and Coerce" behavior mismatch between host and FPGA execution for FXP types
The "In Range?" output behavior or the "In Range and Coerce" function doesn't match the desktop for cases where FXP inputs are rounded to the 64-bit word length limit (due to non-aligned or disjoint input types). LabVIEW FPGA rounds the inputs to the output type before doing the comparisons, whereas the desktop does a true numeric comparison before coercing to the output type.

Workaround: Use coerce inputs to the same type before passing them to the "In Range and Coerce" function to force the same behavior.

Reported Version: 2011    Resolved Version: N/A    Added: 12/14/2012
401588

Return
Controls/Indicators with Unsupported Data Types Inside a Diagram Disable Structure Causes Internal Compilation Error
A control or indicator with an unsupported data type (e.g., Double) inside the disabled case of a diagram disable structure (or conditional disable structure) will cause an internal error at compile time.

Workaround: Remove all controls or indicators with unsupported data types from the block diagram.

Reported Version: 2012    Resolved Version: 2014    Added: 04/05/2013
389331

Return
All Spartan6 Block RAM instantiations use a 36bit data width
When using the Block RAM in a Spartan6 FPGA target, all data types will consume 36 bits of RAM (72 bits for 64bit data types).

Workaround: For smaller data types, use the Join primitives to pack numbers into 32bit wide chunks to ensure more efficient Block RAM utilization. When reading the data back, use the Split primitive, or the Number to Boolean Array and Array Index functions to access the desired element.

Reported Version: 2011    Resolved Version: N/A    Added: 07/17/2013
409860

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The LabVIEW FPGA Module Release and Upgrade Notes incorrectly claim that Xilinx does not officially support Windows 7
According to Xilinx, Windows 7 is a supported OS for the ISE toolchain, which is included with the LabVIEW FPGA Module. For more information on Xilinx ISE OS support, please see http://www.xilinx.com/ise/ossupport/index.htm.

Workaround: N/A

Reported Version: 2013    Resolved Version: N/A    Added: 07/17/2013
411550

Return
The In Range and Coerce function may return an incorrect result for some Fixed-Point configurations
When using Fixed-Point numbers with extremely large deltas (e.g., Word Length: 1, Integer Word Length 900) the In Range and Coerce function may return an invalid value. Typically, In Range will return a True value incorrectly.

Workaround: Use the TypeCast function to convert the FXP number to an Integer before using the In Range and Coerce function for FXP configurations with very large deltas.

Reported Version: 2012    Resolved Version: N/A    Added: 07/17/2013
412467

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Execution on the Desktop Computer will fail for Dynamic Dispatch VIs containing Handshake Nodes
Attempting to Simulate a project with a Handshake Node inside a Dynamic Dispatch VI will fail with the following error: "The handshake is outside a single-cycle Timed Loop. Handshake items are supported only inside a single-cycle Timed Loop."

Workaround: Use a conditional disable structure to use two Register primitives instead of Handshake Nodes during simulation

Reported Version: 2013    Resolved Version: 2014    Added: 07/17/2013
412610

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The LabVIEW FPGA Linux Compile Worker hangs during configuration on RHEL 5.6 x64 (Japanese)
When configuring the server for the LabVIEW FPGA Linux Compile Worker on a Japanese version of RHEL, the utility may hang when the configure button is pressed.

Workaround: Install an English version of Linux Red Hat EP 5.6 64bit. An additional unconfirmed workaround is to set the keyboard settings to QWERTY.

Reported Version: 2012    Resolved Version: N/A    Added: 07/17/2013
413443

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The IP Integration Node configuration window may hang
If the IP Integration node references a file whose path on disk is longer than 140 characters will hang an underlying dependency of the IP Integration Node.

Workaround: Restrict the file path length of any files referenced by the IP Integration node to 140 characters

Reported Version: 2012    Resolved Version: N/A    Added: 07/17/2013
413605

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FIFO Depth may be coerced to a value lower than specified without alerting the user
If a FIFO is created on a target that allows very large FIFO depths, and is then moved to a target whose FPGA only supports smaller FIFOs, the LabVIEW FPGA Module will coerce the FIFO size to an appropriate size for the new target. Depending on the target, the user may not be notified of the change.

Workaround: N/A

Reported Version: 2013    Resolved Version: 2014    Added: 07/17/2013
414753

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The Desktop Execution Node may throw error 1193 when attempting to connect to a running FPGA VI
If the Desktop Execution Node is used to access a Boolean Control whose mechanical action is set to Latch, the configuration dialog will throw error 1193.

Workaround: Stop execution of the FPGA VI before configuring the Desktop Execution Node.

Reported Version: 2013    Resolved Version: 2014    Added: 07/17/2013
392441

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Statically referenced FPGA VIs must be reconfigured if upgraded to LabVIEW 2013
If a statically referenced FPGA VI is used in the host VI, and then upgraded to LabVIEW 2013, Error -52005, Invalid Parameter, will be thrown.

Workaround: Reconfigure the Open Fpga VI Reference and reset the path to the bitfile.

Reported Version: 2013    Resolved Version: N/A    Added: 07/19/2013
393669

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Switching the order of the Input Terminals on the SCTL causes a compile error.
Changing the order of the Input Clock and Error Input terminals on the Single Cycle Timed Loop will result in a compile error.

Workaround: Leave the Input Clock terminal as the first input.

Reported Version: 2012    Resolved Version: 2014    Added: 07/19/2013
401546

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Memory Item Simulation may not match in hardware behavior
It is possible to successfully simulate a memory item set to "Never Arbitrate" and then accessed simultaneously by two different Read Methods. This will not work in hardware, and may cause compilation failures

Workaround: N/A

Reported Version: 2012    Resolved Version: N/A    Added: 07/19/2013
401659

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Having mismatched versions of the LabVIEW FPGA Compile Server and Client produces a confusing error message
If the 2012 version of the Compile Server is installed, and attempts to compile to a 2013 Client, the user will receive the following error: An error occurred attempting to connect to this compile server. Details: NI-Farm: Cannot communicate with the NI-Farm server using the specified communication protocol.

Workaround: Install the 2013 version of the NI Compile Server.

Reported Version: 2012    Resolved Version: N/A    Added: 07/19/2013
403070

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The LabVIEW FPGA Compile Worker may fail to shutdown properly
If a Xilinx process hangs during compilation, then the FPGA Compile worker may fail to shutdown properly.

Workaround: Manually kill the hung Xilinx process

Reported Version: 2012    Resolved Version: N/A    Added: 07/19/2013
403661

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Changing the label of a Control or Indicator on your LabVIEW FPGA VI may cause the Desktop Execution Node to throw an error.
If you change the label of a control or indicator on the Front Panel of your FPGA VI that is part of a Desktop Execution Node's configuration, then the Desktop Execution Node will report that the data type of the resource has changed the next time it is run.

Workaround: Open the Desktop Execution Node configuration window, and press the OK button.

Reported Version: 2013    Resolved Version: 2014    Added: 07/19/2013
404665

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The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set
According to the LabVIEW FPGA help documentation, the FIFO.configure method will clear the contents of the host-side FIFO buffer. This is not true if the FIFO.configure method does not change the "Actual Depth" of the host-side FIFO.

Workaround: Use FIFO.Stop and FIFO.Start to clear the host-side FIFO buffer.

Reported Version: 2012 SP1    Resolved Version: N/A    Added: 07/19/2013
409261

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The Waveform Sampling Probe Window transition buttons may not behave as expected on 1st press
If the vertical yellow line is not already displayed on the graph, then the first press of the transition buttons in the Waveform Sampling Probe window will appear to do nothing.

Workaround: Click on the graph before using the buttons, or press the button twice.

Reported Version: 2013    Resolved Version: 2014    Added: 07/19/2013
409275

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QuestaSim may crash unexpectedly
Certain designs may cause QuestaSim to crash, even with designs that correctly simulate in ISIM.

Workaround: Upgrade to QuestaSim 10.0d or 10.2b

Reported Version: 2013    Resolved Version: 2014    Added: 07/19/2013
410377

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Simulating a FPGA VI that contains IP Integration Nodes may lock up LabVIEW
Simulating a FPGA VI (in both My Computer and FPGA Contexts) that contains IP Integration Nodes may cause a dialog that states that Xilinx is out of memory or LabVIEW may lock up. This only occurs if users start and stop the VI multiple times or has a Host VI that opens, runs, and closes the VI multiple times. Cause: Memory leaks in third-party tools cause the IP Integration Node to leak memory during its initialization routines. Running this initialization routine multiple times can cause the system to run out of memory causing the third party tools to error out or crash, resulting in LabVIEW becoming unresponsive.

Workaround: Avoid simulating multiple IP Integration Nodes and/or avoid simulating your FPGA VI multiple times in the same instance of LabVIEW. Shutdown LabVIEW to allow the third party tools to release the leaked memory.

Reported Version: 2013    Resolved Version: N/A    Added: 07/19/2013
410716

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The host computer may think the LabVIEW FPGA VI needs to be compiled erroneously
If a LabVIEW FPGA VI uses Object Oriented Programming, then LabVIEW will notify you that the FPGA VI needs to be compiled (erroneously) when the host is run.

Workaround: Open the LabVIEW FPGA VI before running the host. Having the FPGA VI open when running the host prevents this error.

Reported Version: 2013    Resolved Version: 2014    Added: 07/19/2013
364903

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Xilinx Coregen Nodes may fail configuration on slow PCs
Xilinx Coregen configuration may return the following error on slow PCs: Error 7 occurred at Open/Create/Replace File in MD5Checksum File.vi->niFpgaXIPINIsFuse2Needed.vi->niFpgaXIPINConfPage1.vi Possible reason(s): LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.

Workaround: N/A

Reported Version: 2012    Resolved Version: N/A    Added: 07/22/2013
367915

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Removal of Implicit Enable Signals in SCTL causes unexpected DMA FIFO reset behavior
When a Single Cycle Timed Loop enables the Removal of Implicit Enable Signals, the VIs clocking behavior changes so that the VI's clock does not run until the VI is run. Any DMA FIFOs within this SCTL will have the portion of the FIFO inside this clock domain reset immediately when the clock begins. While the FIFO is resetting (approximately 2 clock cycles), any data written to the DMA FIFO from this time domain will be lost.

Workaround: N/A

Reported Version: 2012    Resolved Version: 2014    Added: 07/22/2013
382051

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Arithmetic on an Array of Clusters containing an Array of Numerics fails to compile inside an SCTL
Performing an arithmetic operation (e.g. addition) in a Single Cycle Timed Loop on a fixed size array containing a cluster that contains a fixed size array of Numerics incorrectly produces a code-gen error stating that the arithmetic operation cannot be performed in a Single Cycle.

Workaround: Index, un-bundle, and index the desired value before passing it into the arithmetic function.

Reported Version: 2012 SP1    Resolved Version: 2014    Added: 07/22/2013
381497

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Local variable read connected to indicator of subVI in Single Cycle Timed Loop behaves different in simulation than in hardware
In the FPGA context, a subVI in a single cycle timed loop which contains an indicator that returns a read from a local variable behaves differently in simulation than in hardware execution. The data from the local variable read should be delayed one cycle to be in accordance with how it behaves in hardware.

Workaround: Enforce data flow by ordering the local variable write followed by the local variable read connected to the indicator.

Reported Version: 2012    Resolved Version: 2014    Added: 11/11/2013
420143

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Type def FPGA refnum controls with a label containing carriage returns breaks refnum wire
In an FPGA host application, a type defined FPGA refnum control with a carriage return in it's label will break the refnum wire on the block diagram.

Workaround: Don't use carriage returns in the label for FPGA refnum controls.

Reported Version: 2013    Resolved Version: 2014    Added: 11/11/2013
425132

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Installation of LabVIEW FPGA 2013 and NI-RIO 13.0 breaks the FPGA project wizard in earlier versions of LabVIEW FPGA installed on the same computer
If you have a versions of LabVIEW FPGA installed that is 2012 SP1 or earlier and then install LabVIEW FPGA 2013 and NI-RIO 13.0, the FPGA project wizard may be broken in the earlier versions of LabVIEW.

Workaround: If the wizard is needed for both versions, isolate the installations from one another on separate drives or on separate machines (real or virtual).

Reported Version: 2012 SP1    Resolved Version: N/A    Added: 11/11/2013
434094

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Using a homogenous cluster as the x input to an "In Range and Coerce" primitive may cause compilation errors.
When a homogeneous cluster is used as the x input to an "In Range and Coerce" primitive and the "Coerced(x)" output is not wired to anything, HDL errors may occur during compilation.

Workaround: Wire an indicator to the "Coerced(x)" output of the primitive.

Reported Version: 2013    Resolved Version: N/A    Added: 11/11/2013

Document last updated on 1/31/2014

Glossary of Terms

 

  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com.  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).