NI Vision FPGA Function Support and Compatibility

Updated May 2, 2023

Overview

This tutorial lists the Vision FPGA IPs supported in the Vision Development Module as well as its FPGA target compatibilities. Reference this document to ensure that the FPGA functionality, architecture and external memory requirement you need is supported on the target you are compiling on.

List of supported FPGA functions
Supported Vision FPGA Targets
IP Processing Architecture Definition
Additional Resources

List of supported FPGA functions

This table lists all the current supported Vision FPGA functions. It details which processing architecture and data types are supported as well as whether external memory is required.

	Vision IP	IP Architecture	Supported Data types	External Memory Requirement
Image Management	Cast	x1, x8	U1, U8, U16, RGB32, HSL32	N/A
	Vision FPGA Sync	x1, x8		N/A
	Vision FPGA Sync (External Memory)	x1, x8		External Memory with Data Width of 128 bits (x1) External Memory with Data Width of 512 bits (x8)

Color Utilities	Extract Color Plane	x1, x8	RGB32, HSL32	N/A
	Bayer to RGB	x1, x8	U8	N/A
	RGB to Color	x1, x8	RGB32	N/A
	Integer to Color	x1, x8	U32	N/A

Color Processing	Color Histogram	x1	RGB32, HSL32	N/A
	Color Threshold	x1, x8	RGB32, HSL32	N/A
	Color BCGLookup	x1, x8	RGB32	N/A

Morphology	Binary	x1, x8	U1	N/A
	Gray	x1, x8	U8	N/A

Filters	Convolute (No Mask)	x1, x8	U8, U16	N/A
	Convolute	x1	U8, U16	N/A
	Low Pass (No Mask)	x1, x8	U8, U16	N/A
	Low Pass	x1	U8, U16	N/A
	Nth Order	x1, x8	U8, U16	N/A
	Edge Detection (Differentiation, Gradient, Prewitt, Roberts, Sigma, Sobel)	x1, x8	U8, U16	N/A

Processing	BCG Lookup	x1, x8	U8	N/A
	Inverse	x1, x8	U8, U16	N/A
	Theshold	x1, x8	U8, U16	N/A
	Equalize	x1	U8, U16	External Memory with Data Width of 128 bits or 512 bits
	Flat Field Correction	x1, x8	U8, U16	N/A
	Local Threshold	x1, x8	U8, U16	External Memory with Data Width of 512 bits
	AutoBThreshold	x1, x8	U8	External Memory with Data Width of 512 bits

Operators	Add	x1, x8	U8, U16, RGB32, HSL32	N/A
	Subtract	x1, x8	U8, U16, RGB32, HSL32	N/A
	Multiply	x1, x8	U8, U16, RGB32, HSL32	N/A
	Divide	x1, x8	U8, U16, RGB32, HSL32	N/A
	Absolute Difference	x1, x8	U8, U16, RGB32, HSL32	N/A
	Muldiv	x1, x8	U8, U16, RGB32, HSL32	N/A
	Modulo	x1, x8	U8, U16, RGB32, HSL32	N/A
	And	x1, x8	U1,U8, U16, RGB32, HSL32	N/A
	Or	x1, x8	U1,U8, U16, RGB32, HSL32	N/A
	Xor	x1, x8	U1,U8, U16, RGB32, HSL32	N/A
	LogDiff	x1, x8	U8, U16, RGB32, HSL32	N/A
	Mask	x1, x8	U8, U16, RGB32, HSL32	N/A
	Compare	x1, x8	U8, U16, RGB32, HSL32	N/A

Manipulation
	Extract	x1, x8	U1,U8,U16,RGB32,HSL32	N/A

Analysis	Histogram	x1, x8	U8, U16	N/A
	Quantify	x1	U8, U16	N/A
	Centroid	x1, x8	U8, U16	N/A
	Linear Averages	x1, x8	U8, U16	N/A
	Line Profile	x1	U8, U16, RGB32, HSL32	N/A
	Particle Analysis	x1, x8	U1	N/A

Caliper	Simple Edge	x1	U8, U16	N/A

Region of Interest	ROI to Mask	x1, x8	U8, U16, RGB32, HSL32	N/A

Image Transfer	FIFO to Pixel Bus	x1, x8	U8, U16, RGB32, HSL32	N/A
	Pixel Bus to FIFO	x1, x8	U1,U8, U16, RGB32, HSL32	N/A

Supported Vision FPGA Targets

In order to determine which FPGA targets can be used with which IP architecture and external memory requirement, refer to this following table:

FPGA Targets	IP Architecture	Number of External Memory Banks	External Memory Data Width (bits)
Virtex 5
PCIe-1473R/1473R-110T	x1	2	128
PXIe-7951/52/53/54*	x1	2	64
PXIe-7961/62/65*	x1	2	128
Spartan 6
CVS 1457/58/59	x1	N/A	N/A
IC 3120/21	x1	N/A	N/A
sbRIO 9606/07/26/27/36/37	x1	N/A	N/A
Zync
cRIO-9068	x1	N/A	N/A
myRIO, sbRIO-9651	x1	N/A	N/A
Kintex 7
cRIO-9030/31/33/34	x1, x8	1	128
IC-317X	x1, x8	1	512
PXIe-7975/76*	x1, x8	1	512
PCIe-1477	x1, x8	1	512
Kintex Ultrascale
PXIe-7912/15**	x1, x8	2	256

*FlexRIO cards are used with 1483 Adapter Module for Camera Link Acquisitions

**Kintex Ultrascale FlexRIO cards are used for co-processing

Note: On targets with two memory banks, two instances of these IPs can be used, provided the memory elements of each instance are in different banks. For targets that only have one memory bank, we recommend only using one instance of the IP.

IP Processing Architecture Definition

For Vision FPGA functions, there are currently two different processing architectures available. You can either process one pixel or eight pixels at a time per single cycle timed loop.

Multi-pixel processing was added in Vision Development Module 2016 to address higher throughput applications and increase parallelism. This new architecture allows to increase throughput and decrease processing time to finally match camera acquisition bandwidth. As an example, at a rate of 120MHz processing eight 8 bit pixels at a time, we can achieve a throughput of 960MB/s which is higher than the maximum Camera Link throughput.

Additional Resources

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