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This document contains the LabVIEW Communications System Design Suite 2.0 known issues that were discovered before and since the release of LabVIEW Communications System Design Suite 2.0. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
The following items are known issues in LabVIEW Communications System Design Suite 2.0 sorted by Date.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 563511 Return | Some chassis slots appear blank in SystemDesigner with no description why Chassis such as the PXIe-1062Q include slots that may not be supported in LabVIEW Communications. These slots still show on SystemDesigner but there is no ability to interact with them and no indication why. Workaround: Blank chassis slots indicate an unsupported slot in LabVIEW Communications.
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| 571822 Return | A crash may occur when trying to compile a bitfile from a previous version's project if the FPGA target was copied Trying to compile a VI under an FPGA target that was copied and pasted on SystemDesigner in a previous version may cause an unexpected crash. Workaround: Rebuild the targets on SystemDesigner from new rather than copying and pasting.
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| 572029 Return | Right-Click and Context Palette nodes get cropped when text size to 125% If the user has their system to show text at 125%, the nodes in the Right-click and Context Palettes may not display correctly. Workaround: Adjust operating system settings to display text at a setting less than 125%.
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| 572838 Return | Reported Compile Duration may be incorrect after reconnecting to compilation If a disconnection and re-connection occurs during an FPGA compilation, then Total Duration and Compile Time information may be displayed incorrectly on the bitfile document. Workaround: This issue only affects Total Duration and Compile Time displayed on the bitfile document. The elapsed time of each compile step is still correct and this issue does not affect functionality of the actual compilation process.
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| 572970 Return | Previous version VIs will not mutate correctly if the VI is placed on SystemDesigner without any targets A VI placed on SystemDesigner without any targets in LabVIEW Communications 1.1, and earlier, will not mutate correctly when importing into newer versions. Workaround: Place the VI within the correct target context prior to upgrading the project.
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| 576267 Return | Under certain conditions, adding a GCDL document to the VI under a PC target will display the icon incorrectly When a GCDL document exists under two FPGA targets and is added to a VI under a PC target, the icon will display incorrectly. Workaround: Ensure that the GCDL is within a VI for a valid target.
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| 577273 Return | Using Save All after modifying both a VI and a Typedef may cause the VI to appear to require an additional save Since Typedefs update usages on saves, there can be a race condition where the VI is saved before the Typdef. This shows that the VI requires an additional save despite being saved already. Workaround: The changes will be saved so there is no loss of data. However, saving files individually, or making changes to Typedefs and related VIs separately, can help avoid the need for additional saves.
| |||||
| 578591 Return | "Conflicting Items Exist" dialog pops up in error during project reload if the running VI was added to the project before the project was saved When loading a project that contains a Real-Time target, there is an attempt to connect ,and attach, to any already running VIs on the target. When the VI in the project matches the VI running on the target, it should seamlessly attach and the VI's panel state should reflect the current state of the running VI on the target. However, if the VI was created, or added, to the project before the project had ever been saved, the attach always fails and a conflict dialog is displayed. Workaround: Always save the project before adding any VIs.
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| 584478 Return | Comparison mode setting is not preserved when converting LabVIEW comparison nodes with waveforms as inputs When converting VIs which compare waveforms using the following nodes: IsGreater, IsGreaterOrEqual, IsLess and IsLessOrEqual, the Comparison Mode setting is not preserved. It will be set to the default value of "Compare Elements". If the original VI has "Compare Aggregates" set, the converted VI will have a broken wire output from the comparison node. This is because the data type of the output is not the same for the two modes. Workaround: Visit each comparison node with a broken wire and set the "Comparison Mode" to "Compare Aggregates".
| |||||
| 584767 Return | Some UI elements in the LabVIEW Communications environment may not display correctly using custom DPI settings Some UI elements may display incompletely if using a custom Windows DPI setting of 125%, or similar. Workaround: Use default DPI settings.
| |||||
| 587454 Return | Including a large number of files in the project at once can cause LabVIEW Communications to hang Adding a large number of files to the project from the Navigation Pane can cause the application to hang or become unresponsive for a time. Workaround: Minimize the number of files added at the same time. Add smaller groups of files more often rather than all at once.
| |||||
| 587522 Return | Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail. Workaround: Do not modify the build spec during compilation.
| |||||
| 589526 Return | Large local FIFOs may cause unsuccessful compilations Creating local FIFOs near the maximum allowable sizes may cause compilations to fail with the message "There is a problem with one or more of the VIs associated with the compile". Workaround: Reduce the total size of the FIFO .
| |||||
| 590787 Return | DRAM Access Time should not be set to a value of 1 DRAM Access Time should be set to any positive number other than 1 in order to work properly. Workaround: DRAM Access Time should be set to any positive number other than 1 in order to work properly.
| |||||
| 591575 Return | MRD QR Decomposition example may display mismatched data values When running the MRD QR Decomposition example, and viewing the data comparison from FPGA to host, there may be inconsistent values displayed. This is due to data coercion. Workaround: Change the Q and R array indicators to the Double data type to get rid of the coercions.
| |||||
| 592178 Return | Editing subVI terminals while that subVI is set to List View in a calling VI can cause the project to crash A subVI called from another VI can have its Visual Style set to either Icon or List at the callsite. When set to List, calling VIs may not be able to properly propagate terminal edits made to that subVI. This can result in subsequent project crashes when trying to open the calling VI. Workaround: Switch subVI calls to Icon view instead of List view when rearranging terminals.
| |||||
| 594363 Return | Charts will not display a cluster of Fixed Point data types Charts will not correctly display data for clusters containing one, or more, Fixed Point (FXP) data types. No error, or warning, is displayed but a subsequent crash may occur after VI execution. Charts will display correctly for Fixed Point data types not bundled into a cluster. Workaround: Use other data types in place of Fixed Points if bundling clusters of Chart data.
| |||||
| 595935 Return | Profiling fixed-point data for a CDB array may cause the application to hang If a design includes an array of complex double floating-point data types, and the "Profile Fixed Point Data" option is enabled for the VI, then running the VI in simulation may cause the application to hang and become unresponsive. Workaround: Split CDB arrays into real and imaginary arrays for fixed-point profiling.
|
The following items are known issues in LabVIEW Communications System Design Suite 2.0 sorted by Category.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| Example Programs | ||||||
| 591575 Return | MRD QR Decomposition example may display mismatched data values When running the MRD QR Decomposition example, and viewing the data comparison from FPGA to host, there may be inconsistent values displayed. This is due to data coercion. Workaround: Change the Q and R array indicators to the Double data type to get rid of the coercions.
| |||||
| LabVIEW Project | ||||||
| 576267 Return | Under certain conditions, adding a GCDL document to the VI under a PC target will display the icon incorrectly When a GCDL document exists under two FPGA targets and is added to a VI under a PC target, the icon will display incorrectly. Workaround: Ensure that the GCDL is within a VI for a valid target.
| |||||
| 577273 Return | Using Save All after modifying both a VI and a Typedef may cause the VI to appear to require an additional save Since Typedefs update usages on saves, there can be a race condition where the VI is saved before the Typdef. This shows that the VI requires an additional save despite being saved already. Workaround: The changes will be saved so there is no loss of data. However, saving files individually, or making changes to Typedefs and related VIs separately, can help avoid the need for additional saves.
| |||||
| 578591 Return | "Conflicting Items Exist" dialog pops up in error during project reload if the running VI was added to the project before the project was saved When loading a project that contains a Real-Time target, there is an attempt to connect ,and attach, to any already running VIs on the target. When the VI in the project matches the VI running on the target, it should seamlessly attach and the VI's panel state should reflect the current state of the running VI on the target. However, if the VI was created, or added, to the project before the project had ever been saved, the attach always fails and a conflict dialog is displayed. Workaround: Always save the project before adding any VIs.
| |||||
| 587454 Return | Including a large number of files in the project at once can cause LabVIEW Communications to hang Adding a large number of files to the project from the Navigation Pane can cause the application to hang or become unresponsive for a time. Workaround: Minimize the number of files added at the same time. Add smaller groups of files more often rather than all at once.
| |||||
| Miscellaneous | ||||||
| 563511 Return | Some chassis slots appear blank in SystemDesigner with no description why Chassis such as the PXIe-1062Q include slots that may not be supported in LabVIEW Communications. These slots still show on SystemDesigner but there is no ability to interact with them and no indication why. Workaround: Blank chassis slots indicate an unsupported slot in LabVIEW Communications.
| |||||
| 572029 Return | Right-Click and Context Palette nodes get cropped when text size to 125% If the user has their system to show text at 125%, the nodes in the Right-click and Context Palettes may not display correctly. Workaround: Adjust operating system settings to display text at a setting less than 125%.
| |||||
| 572838 Return | Reported Compile Duration may be incorrect after reconnecting to compilation If a disconnection and re-connection occurs during an FPGA compilation, then Total Duration and Compile Time information may be displayed incorrectly on the bitfile document. Workaround: This issue only affects Total Duration and Compile Time displayed on the bitfile document. The elapsed time of each compile step is still correct and this issue does not affect functionality of the actual compilation process.
| |||||
| 584767 Return | Some UI elements in the LabVIEW Communications environment may not display correctly using custom DPI settings Some UI elements may display incompletely if using a custom Windows DPI setting of 125%, or similar. Workaround: Use default DPI settings.
| |||||
| 587522 Return | Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail Changing the build spec from "Bitfile" to "None" during compilation will cause the compilation to fail. Workaround: Do not modify the build spec during compilation.
| |||||
| 589526 Return | Large local FIFOs may cause unsuccessful compilations Creating local FIFOs near the maximum allowable sizes may cause compilations to fail with the message "There is a problem with one or more of the VIs associated with the compile". Workaround: Reduce the total size of the FIFO .
| |||||
| 590787 Return | DRAM Access Time should not be set to a value of 1 DRAM Access Time should be set to any positive number other than 1 in order to work properly. Workaround: DRAM Access Time should be set to any positive number other than 1 in order to work properly.
| |||||
| 592178 Return | Editing subVI terminals while that subVI is set to List View in a calling VI can cause the project to crash A subVI called from another VI can have its Visual Style set to either Icon or List at the callsite. When set to List, calling VIs may not be able to properly propagate terminal edits made to that subVI. This can result in subsequent project crashes when trying to open the calling VI. Workaround: Switch subVI calls to Icon view instead of List view when rearranging terminals.
| |||||
| 594363 Return | Charts will not display a cluster of Fixed Point data types Charts will not correctly display data for clusters containing one, or more, Fixed Point (FXP) data types. No error, or warning, is displayed but a subsequent crash may occur after VI execution. Charts will display correctly for Fixed Point data types not bundled into a cluster. Workaround: Use other data types in place of Fixed Points if bundling clusters of Chart data.
| |||||
| 595935 Return | Profiling fixed-point data for a CDB array may cause the application to hang If a design includes an array of complex double floating-point data types, and the "Profile Fixed Point Data" option is enabled for the VI, then running the VI in simulation may cause the application to hang and become unresponsive. Workaround: Split CDB arrays into real and imaginary arrays for fixed-point profiling.
| |||||
| Upgrade - Migration | ||||||
| 571822 Return | A crash may occur when trying to compile a bitfile from a previous version's project if the FPGA target was copied Trying to compile a VI under an FPGA target that was copied and pasted on SystemDesigner in a previous version may cause an unexpected crash. Workaround: Rebuild the targets on SystemDesigner from new rather than copying and pasting.
| |||||
| 572970 Return | Previous version VIs will not mutate correctly if the VI is placed on SystemDesigner without any targets A VI placed on SystemDesigner without any targets in LabVIEW Communications 1.1, and earlier, will not mutate correctly when importing into newer versions. Workaround: Place the VI within the correct target context prior to upgrading the project.
| |||||
| 584478 Return | Comparison mode setting is not preserved when converting LabVIEW comparison nodes with waveforms as inputs When converting VIs which compare waveforms using the following nodes: IsGreater, IsGreaterOrEqual, IsLess and IsLessOrEqual, the Comparison Mode setting is not preserved. It will be set to the default value of "Compare Elements". If the original VI has "Compare Aggregates" set, the converted VI will have a broken wire output from the comparison node. This is because the data type of the output is not the same for the two modes. Workaround: Visit each comparison node with a broken wire and set the "Comparison Mode" to "Compare Aggregates".
| |||||