| ID | Known Issue |
|---|
392126
| The niVST Calibration.lvlib:Self-Calibrate.vi leaks memory when loading and unloading
When using Self-Calibrate VI from the NI VST Calibration palette to self-calibrate the NI PXIe-5644R or NI PXIe-5645R, a memory leak may occur when loading and unloading the VI repeatedly.
Workaround: Keep the Self-Calibrate VI in memory. For example, in your top-level VI, create a "dummy" subVI that includes one instance of the Self-Calibrate VI to keep the Self-Calibrate VI loaded in memory. For applications that optimize memory usage where it is not acceptable to keep the Self-Calibrate VI in memory, you can minimize the memory leak by keeping a Timed Loop in memory. A memory leak will still exist, but it will be considerably smaller.
| Reported Version: Design Library 2012.1 | | Resolved Version: N/A | | Added: 04/05/2013 |
|
363009
| The NI PXIe-5644R or NI PXIe-5645R device may occasionally appear outside the chassis in MAX when the device is installed for the first time
The NI PXIe-5644R or NI PXIe-5645R device may occasionally appear outside the chassis in Measurement & Automation Explorer (MAX) when the hardware/software is installed for the first time. The device should still function properly.
Workaround: Restart the machine to get the device to appear in MAX properly.
| Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
|
N/A
| Some VIs of the Configuration Instrument Design Library have new required inputs
VIs that use subVIs from the Configuration Instrument Design Library might be broken after updating to instrument design libraries 2012.1. The following VIs have new required inputs:
- RF In Create Baseband ADC Settings VI
- RF In Create Settling Settings VI
- RF In Create Cal Synthesizer Settings VI
- RF Out Create Settling Settings VI
- RF Out Create Baseband DAC Settings VI
Workaround: Wire the new required inputs.
| Reported Version: Design Library 2012.1 | | Resolved Version: N/A | | Added: 04/10/2013 |
|
385430
| niVST Self-Calibrate.vi cannot be found
When using the NI PXIe-5644R or NI PXIe-5645R and upgrading to instrument design libraries 2012.1, niVST Self-Calibrate.vi is missing because it has been moved and renamed. Replace the missing VI with the Self-Calibrate VI located on the NI VST Calibration palette or at <LabVIEW>\instr.lib\niVST\Calibration\SelfCal\Self-Calibrate.vi for your device.
Workaround: Replace existing calls to niVST Self-Calibrate.vi with a call to Self-Calibrate.vi.
| Reported Version: Design Library 2012.1 | | Resolved Version: N/A | | Added: 04/05/2013 |
|
364518
| Error –52018. A hardware failure has occurred. The operation could not be completed as specified
This error may occur when an instrument design VI accesses elements of an FPGA VI that are inside a Single Cycle Timed Loop (SCTL) that does not have a running clock. In this case, the problem is not a hardware failure and can be fixed by enabling the clock of the SCTL.
Workaround: Ensure that the SCTL clocks are running before calling the VI that returns the error.
| Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
|
404057
| Cannot create a new project with a file name prefix from the VST Streaming sample project
When creating a new project from the VST Streaming sample project, if you enter a File Name Prefix in the Configure new project dialog box, error 1026, LabVIEW: VI Reference is invalid., occurs and project creation fails.
Workaround:
- Download the postcopyscripting2 Zip file from the Downloads section of this document.
- Unzip the file and replace PostCopyScripting2.vi, located in <Program Files>\National Instruments\LabVIEW 2012\ProjectTemplates\Source\VST\Simple VST Streaming (NI 5644R, NI 5645R)\scripting\, with the new PostCopyScripting2 VI.
| Reported Version: Design Library 1.1 | | Resolved Version: Design Library 13.5 | | Added: 04/30/2013 |
|
365340
| Running a VST sample project FPGA VI on a development computer with simulated I/O context causes LabVIEW to hang
Running a VST Sample Project FPGA VI on the development computer with simulated I/O context causes LabVIEW to hang because of the way LabVIEW FPGA allocates and uses the DRAM memory primitive when executing in the development computer context.
Workaround: There is no workaround to achieve full functionality, that is, to achieve the same waveform and record memory size available when running on hardware. However, you can use the following instructions to work around the LabVIEW memory issue:- In the FPGA Target in your LabVIEW project, navigate to Memory/FIFOs»Acquisition»acq.data memory 0.
- Right-click acq.data memory 0 and select Properties.
- Under the General category, change the Requested number of elements to a smaller number, for example, 65,536.
- Repeat steps 2 and 3 for Memory/FIFOs»Generation»wfm seq.data memory 0.
- Change the memory size (128-bit elements) value in Acquisition.lvclass»Private»Constants.vi.
- Change the waveform memory size (num of 128-bit elements) value in Generation.lvclass»Private»Constants.vi.
Note: There is no guarantee that the rest of the sample project will work after you work around the LabVIEW memory issue.
| Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
|
364860
| A deadlock can occur when creating two peer-to-peer streams between two devices in opposite directions concurrently
Workaround: To avoid the deadlock, serialize the calls to the niP2P Create Peer to Peer Stream VIs.
| Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
|
356334
| External Calibration sessions that are not closed can lock up the device
If the External Calibration session is not closed, for example, if execution aborts before the call to the Close External Calibration VI, the device becomes unusable. Even new calls to Initialize External Calibration fail.
Workaround: To release the session, unload the External Calibration DLL or close the process that called the External Calibration DLL. Otherwise, restart the computer.
| Reported Version: Design Library 1.0 | | Resolved Version: Design Library 13.5 | | Added: 08/28/2012 |
|
364736
| Waveform Sequencer does not generate any samples if the Set Priming Depth VI is set to a value of 4 samples or less
The Retrieve Waveform Sample FPGA VI of the Waveform Sequencer library does not generate any samples if you set the generation priming depth to a value less than or equal to 4 in the Set Priming Depth VI of the Waveform Sequencer host library.
Workaround: Configure the Set Priming Depth VI to a value of at least 5 samples; otherwise do not call the Set Priming Depth VI. If you do not call the Set Priming Depth VI, the application uses the default priming depth.
| Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
|
369338
| A dialog box prompts you to save a file when you create a VST sample project in localized LabVIEW
The first time you create a VST sample project (Simple VSA/VSG or Simple VST Streaming) in localized LabVIEW after installing instrument design libraries 2012.1, a dialog box prompts you to save niLvFpga_Open_PXIe-5644R.vi or similar.
Workaround: Click Save in the dialog box to continue creating the sample project.
| Reported Version: Design Library 2012.1 | | Resolved Version: N/A | | Added: 04/05/2013 |
|
