NI does not actively maintain this document.
This content provides support for older products and technology, so you may notice outdated links or obsolete information about operating systems or other relevant products.
Each issue appears as a row in the table and includes the following fields:
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 383655 | ADC microport lines can be double driven momentarily The device's ADC and FPGA can momentarily double drive some ADC microport lines. The ADC microport is only tristated after CS_n and RD_n are deasserted AND the ADC detects a rising edge of the serial clock. When a read is performed, the clock is stopped prior to deasserting the CS and RD lines, which leaves the ADC actively driving the data bus. On a following write access, the host code enables the FPGA output driver prior to starting the ADC clock. During this period of time, the FPGA and ADC may drive into each other causing excessive current to flow. Workaround: Alter the ADC microport read/write VI to send an extra clock cycle with CS/RD/WT deasserted ('1') either immediately before or immediately after any write or read transaction to tell the ADC to stop driving the data bus.
| |||||
| 333614 | Issues with LabVIEW 2010 Real-Time If you are using LabVIEW 2010 and are deploying to a LabVIEW Real-Time target and you do not have the full version of LabVIEW Real-Time installed, your device may behave unexpectedly. Workaround: Download and install the LabVIEW Real-Time 2010 f1 Patch.
| |||||
| 137784 | Cannot save the ni5640R Spectrum Analyzer VI for previous versions of LabVIEW. If you use LabVIEW 8.6 and try to save the ni5640 Spectrum Analyzer VI to a previous version of LabVIEW such as LabVIEW 8.5, warnings are returned. Workaround: N/A
| |||||
| 203715 | When you enable and choose a CLIP for the DRAM socket, you cannot successfully compile when some Xilinx Options are all set to High. In LabVIEW 2009 only, when you enable and choose a CLIP for the DRAM socket, you cannot successfully compile when the following Xilinx Options are all set to High: Synthesis Optimization Effort Level Map Overall Effort Level Place and Route Overall Effort Level Workaround: The Xilinx Options page in the FPGA Target Properties page is accessed by right-clicking the target in the Project Explorer window.
| |||||
| 256976 | NI-5640R 1.3 and later includes a new FPGA I/O Node called DAC_Simultaneous_Reset that needs to be added to the target tree in older LabVIEW project files. NI-5640R 1.3 and later includes a new FPGA I/O Node called DAC_Simultaneous_Reset. The node must be added to the target tree in older LabVIEW project files. This node adds a new feature to the configuration loop that makes it easier to reset and synchronize the DACs. Workaround: Complete the following steps to add the node to an earlier LabVIEW project file:
| |||||
| 257253 | Cannot locate FPGA Examples. LabVIEW FPGA examples cannot be located using the NI Example Finder. Workaround: To locate these examples, refer to the table in the Installed Files section of the NI-5640 1.6 Readme or navigate to Start»All Programs»National Instruments»NI-5640R»Examples»<LabVIEW> and then open the FPGA folder.
| |||||
| 257263 | Global variables stored in different locations. Register and Circular Buffer data exchange policies use global variables created by the generated code behind the NI-5640R Asynchronous Programming nodes. If your LabVIEW project has not yet been saved, the global variables are stored on disk in a folder at <LabVIEW>\instr.lib\ni5640R\FPGA\AsyncWires\Globals. After your project is saved, the global variables are stored in a folder named Globals in the same folder where your project is stored. The globals are also placed in a LabVIEW project folder named Generated Globals. Deleting a global from the disk folder breaks the primitives that use it, but does not affect the bitfile produced by a previous compile. Causing that primitive to reconfigure itself also causes it to regenerate the globals. Workaround: N/A
| |||||
| 257592 | Host VIs do not open. Host VIs developed in previous versions of LabVIEW do not run when initially opened in later versions of LabVIEW. For example, if you created a host VI in LabVIEW 8.2.1, the VI does not run when initially opened in any later version of LabVIEW such as LabVIEW 8.5, 8.6, 2009, 2010, or 2011. Similarly, if you created a host VI in LabVIEW 8.6, the VI does not run when initially opened in any later version of LabVIEW such as LabVIEW 2009, 2010, or 2011. Workaround: For instructions about how to upgrade to LabVIEW 2010 or later, refer to the Upgrading the NI-5640R Driver topic of the NI-5640R Help File to run the VI. To upgrade to LabVIEW 2009, complete the following steps to run the VI.
| |||||
| 239701 | ni5640R Configure RTSI.vi does not correctly configure. ni5640R Configure RTSI.vi does not correctly configure RTSI 6 or RTSI 7 on the NI PXIe-5641R. Workaround: N/A
| |||||
| 255638 | Incorrect installation behavior when removing NI-5640R 1.5 and installing NI-5640R 1.4. When removing NI-5640R 1.5 and installing NI-5640R 1.4, the installer tree may display a gray circle with a slash mark on white background for NI-5640R features. Workaround: Complete the following steps to install LabVIEW-specific features.
| |||||
| 309010 | Temperature sensor reads may intermittently return incorrect data under high CPU load. There is a timeout in sending commands to the temperature sensor, thereby causing the incorrect information to be read back. Workaround: Run NI-5640R in LabVIEW 2011. This workaround does not apply to versions of LabVIEW 2010 and earlier.
| |||||
| 144748 | NI 5640R/5641R streaming examples miscalculate rate when using two channels. The NI PCI-5640R and NI PXIe-5651R Stream to Disk example miscalculates the streaming rate when two channels are enabled. The streaming rate is calculated by multiplying the block size with the number of bytes per sample and factoring that value in with the time it takes to fetch data. When two channels are enabled, the block size is doubled for the raw data polymorphic VI to account for two interleaved channels. This compensation is not accounted for in the preceding calculation. Thus, half the rate is reported for streaming statistics. Workaround: N/A
| |||||
| 191505 | Errors when running many of the NI-5640R template VIs and examples in Execute VI on Development with Simulated I/O mode. NI-5640R template VIs (and thereby the FPGA examples) utilize Session to Refnum VI. When run in Execute VI on Development Computer with Simulated I/O mode, NI-RIO read and write VIs may not function properly when using the Session to Refnum VI. Workaround: On your block diagram, place a Diagram Disable Structure around all of the configuration VIs. This allows you to emulate your code.
| |||||
| 256974 | LabVIEW FPGA examples for the NI PCI-5640R and the NI PXIe-5641R are precompiled and configured only for a 32-bit Windows installation where they are installed under the default path, C:\Program Files\ LabVIEW FPGA examples for the NI PCI-5640R and the NI PXIe-5641R are precompiled and configured for a 32-bit Windows installation where they are installed under C:\Program Files\. When installing to a non-default path or when installing on a 64-bit Windows machine (to C:\Program Files (x86)\), the host-side VI must be edited to correctly locate the FPGA bitfile and bind its new path to the session typedef. The FPGA bitfiles do not need to be recompiled.
|
Contact NI regarding this document or issues in the document. If you contact NI in regards to a specific issue, reference the ID number given in the document. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting NI). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Also contact us if you find a workaround for an issue that is not listed in the document.