Users program the FPGA using LabVIEW system design software with the LabVIEW FPGA Module, enabling both LabVIEW-based algorithm capture and VHDL/Verilog integration. Existing LabVIEW libraries can be used to accelerate development with data movement infrastructure, advanced signal processing functions like an ultra-wideband fast Fourier transform (FFT) and parallel resampling algorithms, and managed DMA streaming to host. Designs can be simulated in LabVIEW before compiling locally or through the NI Compile Cloud Service. After the FPGA bitfile is compiled using LabVIEW FPGA and Xilinx Vivado, bitfiles are deployed through LabVIEW on the development machine; by real-time applications, built with LabVIEW or C/C++, running on the controller; or from the device’s flash on power-up. In many FlexRIO designs, logic is clocked at hundreds of megahertz, where it can be more difficult to meet timing constraints. NI recommends that newer LabVIEW FPGA developers start by reviewing the High-performance LabVIEW FPGA Developers Guide for best practices on both timing and resource optimization.
Figure 4: LabVIEW simplifies FPGA programming by providing an integrated, graphical development environment for design, simulation, debugging, and deployment.
Engineers can choose between two FPGA options: a Xilinx Kintex-7 K325T and a larger K410T. For initial development, using the largest FPGA available has significant advantages. Not only does it give the flexibility to add features during development, but it also provides the ability to compile the same code on a larger FPGA, which generally reduces compile times during design, making faster iteration possible. With NI-provided I/O interfaces, LabVIEW FPGA code written for one hardware target can be quickly ported to other NI hardware, even hardware with different FPGAs and I/O capabilities.
Block RAM (kb)
Figure 5: The Controller for FlexRIO features two different Xilinx FPGAs so that users can choose the right part for the application. NI recommends using the largest FPGA for initial development before attempting to optimize the design for deployment.
DRAM is a resource that adds substantial value in multistage signal processing algorithms and data buffering across nondeterministic buses. To make these types of operations possible, all three variants of the Controller for FlexRIO have one 2 GB bank of DDR3 DRAM attached to the FPGA. The DRAM interface has a data width of 512 bits and is efficiently accessed at clock rates up to 166 MHz, which results in a maximum theoretical bandwidth of 10.6 GB/s between the DRAM and the FPGA. Random access reads and writes decrease DRAM throughput, however, NI has benchmarked sequential reads and writes above 9 GB/s. DRAM can be addressed using the LabVIEW Memory Item in LabVIEW FPGA or as a FIFO using the Memory Instrument Design Library (IDL).
Learn how to use DRAM effectively.