Understanding Project Configuration

The project contains several required resources for a successful compilation:

Clocks—The project provides three clocks:

• 160 MHz Clock (derived from PXIe_Clk100): Used as the clock for all signal processing. The VST data clock runs at 156.25 MHz. This coprocessor signal processing of IQ data must run slightly faster at 160 MHz. This ensures that there are no underflows of data due to Aurora protocol overhead. Write the signal processing so that it can run faster than the VST.
  Note The target streaming IP resides within the 160 MHz clock domain for this example. However, there are no restrictions that enforce that IP to be run at that clock rate.
• 40 MHz Register Bus Clock (derived from PXIe_Clk100): The data source and sink modules used to transfer data from/to the VST use the instruction framework to communicate with the host (Windows) application. Custom modules can also use the instruction framework.
• 80 MHz Clock: Used to configure and monitor the MGT links for the Aurora protocol that transfer data between the VST and the coprocessor.

FIFOs—The instruction framework requires a DMA FIFO with a fixed name and the following configuration:

• IQ Data Streaming:
  • Name: reg.host instruction fifo 0
  • Type: Host to Target – DMA
  • Size: 1023 Elements
  • Data Type: U64
• Target Streaming:
  • Name 1: reg.host instruction fifo 1
  • Type: Host to Target – DMA
  • Size: 1023 Elements
  • Data Type: U64
  • Name 2: P2PW u64 1spc.0
  • Type: Peer-to-Peer Writer
  • Size: 1023 Elements
  • Data Type: U64

Software Components

The following components are important in creating and understanding the LabVIEW FPGA code.