Change the Configuration of Sections of a Deployed System Without Undeploying

U64 Data Value Visualization in VeriStand Screen

Added a control to VeriStand Screen which allows U64 data value visualization.

Parallel Execution Mode State Transition Optimizations

Optimized state transitions in the Primary Control Loop when using the Parallel execution mode to allocate more time for model execution.

.vsmodel I/O Performance Improvements

Improved I/O performance in .vsmodel, allowing faster execution when I/O ports are structured with contiguous variables of the same data type.

VeriStand UI Chart Display Rate Optimizations

Improved the responsiveness of the VeriStand UI by optimizing the chart display rate, which allows for better performance when working with a large number of charts.

IP to FPGA Conversion Utility Migrated to .NET 8

The IP to FPGA Conversion Utility has been migrated to .NET 8 from .NET Framework.

Import/Export Channels in Logging Specification

You now can import channels from and export channels to a text file in the logging specification in VeriStand.

VeriStand Model Generation Support for Signals with Protected Models

You now can use signals alongside protected reference models in VeriStand Model Generation support.

VeriStand Mode Generation Support Build Time Improvement

.vsmodels now build significantly faster when large numbers of parameters are present in a data dictionary.

Supporting Automatic Frame Processing for LIN Frames

For LIN frames, VeriStand XNET now supports adding a custom checksum and rolling counter in Automatic Frame Processing (AFP).

Configuring Lowpass Filters for Digital AI Filtering

VeriStand now supports configuring lowpass filters for the NI 4302, 4303, 4304, 4305, 4339, 4480, and 4481 modules.

Running VeriStand on Windows Machine with FIPS

VeriStand can now run on a Windows machine with federal information processing standards (FIPS).

IP to FPGA Conversion Utility Supporting LabVIEW 2025 64-Bit

IP to FPGA Conversion Utility 2025 Q2 now supports LabVIEW 2025 Q1 64-bit.

Configurable Time Axis for VeriStand Chart

VeriStand chart now allows you to configure any monotonically increasing channel as a time axis.

VeriStand Model Generation Support for Block Parameters

Use VeriStand Model Generation Support to access block parameters from Simulink models as model parameters in VeriStand. For more information, refer to How VeriStand Imports Models from the Model Generation Support MATLAB Add-on and the VeriStand Model Generation Support documentation.

Error Message Enhancement

Existing error messages now include more information to help you locate the source of the error.

VeriStand Steps for TestStand

VeriStand Steps for TestStand are sets of custom steps that allow you to automate VeriStand and develop/reuse test sequences for hardware-in-the-loop (HIL) systems.

This product is available for download using NI Package Manager, or at ni.com/downloads. Follow the prompts in NI Package Manager to install VeriStand Steps for TestStand.

Please refer to the VeriStand Steps for TestStand for more information on how to use this application.

LabVIEW 2025 Q1 Support

VeriStand is compatible with LabVIEW 2025 Q1 64-bit. All custom devices, LabVIEW models, and LabVIEW applications that contain the VeriStand API require this LabVIEW version. The VeriStand API will not install in previous versions of LabVIEW.

Enhanced VeriStand Model Generation Support for VeriStand IO Blocks

VeriStand Inport/Outport blocks now supports the enum data type, and can be connected to masked blocks and additional blocks like bus selector.

GCC Compiler Upgrade for VeriStand Model Generation Support

NI GCC Cross-Compiler for NI Linux Real-Time targets toolchain is upgraded to GNU C & C++ Compile Tools x64 2024Q4.

FMI Support for Enum Data Type

Import FMUs with Inports/Outports/Parameters/Signals of type Enum as VeriStand channels.

Enhanced Debug Logging for Simulation Models in Target Log Viewer

Use the Target Log Viewer to understand debug information from FMUs, .vsmodels, and .lvmodels.

Simulink Model Enum Channels on VeriStand Screens

Scalar enum variables from .vsmodel and .fmu (3.0) are visible on VeriStand screens with their type definitions.

IP to FPGA Conversion Utility Supporting LV 2024 64-bit

IP to FPGA Conversion Utility 2024 Q3 now supports LabVIEW 2024 Q1 64-bit.

Support for Custom Reference Designs in HDL Coder Support Package for NI FPGA Hardware

The HDL Coder Support Package for NI FPGA hardware now includes support for custom reference designs, enabling the integration of Simulink models into existing LabVIEW FPGA projects.

VeriStand Model Generation Support for Enum DataType

Use VeriStand Model Generation Support to import Inport/Outport/Signals/Parameter of type Enum from Simulink models as channels.

VeriStand Model Generation Support for VeriStand IO Blocks

Place VeriStand Inport/Outport blocks from VeriStand Model Generation Support anywhere in the subsystem hierarchy in your Simulink model to access them as model Inport/Outport channels.

APIs to Configure ECU Network Cluster

Configure Virtual ECU Clusters programmatically using APIs in the System Definition namespace.

Synopsys Silver FMI 3.0 Virtual ECU Support

Configure and execute Virtual ECUs from Synopsys Silver that follow the FMI 3.0 standard.

LabVIEW 2024 Q1 Support

VeriStand is compatible with LabVIEW 2024 Q1 64-bit. All custom devices, LabVIEW models, and LabVIEW applications that contain the VeriStand API require this LabVIEW version. The VeriStand API will not install in previous versions of LabVIEW.

VeriStand Virtual ECU Toolkit

Use the VeriStand Virtual ECU Toolkit to integrate and execute virtual electronic control units (ECUs) for hardware-in-the loop (HIL) testing. Virtual ECUs allow you to test devices quickly, with a more realistic rest bus simulation, and with less effort for creating the bus simulation.

FMI 3.0 Support

VeriStand can configure and execute FMUs that follow the 3.0 standard. For more information on the support, refer to FMI Support.

Alarm Monitor Displays Trip Message and Value

VeriStand Editor's Alarm Monitor now actively showcases Trip Messages across all three tabs (Active, History, Rules). Furthermore, it actively presents Values within the Active and History tabs. Additionally, the Alarm Log actively records both the Trip Message and Value for comprehensive tracking.

Revamped Launcher Interface

The VeriStand Launcher has undergone a significant transformation, introducing separate tabs for Projects and Learning. To access a collection of preloaded VeriStand projects and educational resources, navigate to the Learning tab. Meanwhile, the Projects tab offers access to Default Projects and enables users to incorporate their custom template projects seamlessly.

VeriStand Model Generation Support for Simulation States

With VeriStand Model Generation Support, you can now preserve the state of a .vsmodel file during execution, allowing for later restoration of the model using the saved state through an XML file. To save and restore states, use the .NET IModel method or the Screen/Workspace.

VeriStand Model Generation Support for Importing Non-Virtual Bus Signals

Use VeriStand Model Generation Support to import non-virtual bus signals from Simulink models as channels. For more information, refer to How VeriStand Imports Models from the Model Generation Support MATLAB Add-on and the VeriStand Model Generation Support add-on documentation.

Python System Definition API

Use niveristand to script system definition (.nivssdf) files for use in the VeriStand Editor and deploy them to the VeriStand Engine. For more information, you can refer to the Getting Started With VeriStand documentation. Note that this feature supports multiple VeriStand versions.

Expanded VeriStand.exe Command Line Options

Use the command line to execute processes in VeriStand, including the ability to now open and close specific files or documents in a project. For more information on specific commands and their functionalities, refer to VeriStand Command Line Options documenatation.

Support for FMU Logging in VeriStand

Set the logging level for FMUs by editing a configuration file to debug failures. For more information on configuring the log levels, refer to FMI Support documentation.

VeriStand Engine Performance

In System Explorer, the new default for the PCL DAQ timing source is Signal From Task (Sample Complete). This default applies to new projects when the timing source is set to DAQ Timing or Automatic Timing and there is a NI-DAQ device with at least one analog input hardware-timed single point channel.

The Signal From Task (Sample Complete) default option sends a tick to the PCL each time the Master DAQ device finishes acquiring an AI channel sample. This setting is beneficial for multiplexed DAQ modules with many channels. The setting has no impact on simultaneous sampled module behavior.

Other VeriStand Engine improvements include loop processing reductions for systems with a high count of channels, mappings, and faultable channels. Large systems, such as those with more than 20,000 channels and 10,000 mappings, can experience HP Loop duration reductions of more than 50 microseconds.

VeriStand Model Generation Support for Importing Signals

Use VeriStand Model Generation Support to import signals from Simulink models as channels. For more information, refer to How VeriStand Imports Models from the Model Generation Support MATLAB Add-on and the VeriStand Model Generation Support add-on documentation.

ESI File Importing

Import an EtherCAT Slave Information (ESI) file into VeriStand using the Scan Engine and EtherCAT Custom Device without installing LabVIEW. To begin importing the ESI file, open System Explorer and navigate to the custom device.

Screen Cluster Arrangement Options

Use additional cluster arrangement options on VeriStand screens to compact the appearance of large cluster hierarchies. To access these options in the VeriStand Editor, navigate to File » Preferences and click Screen to select a cluster arrangement.

IP to FPGA Conversion Utility supporting LV 2023 64-bit

IP to FPGA Conversion Utility 2023 Q2 now supports LabVIEW 2023 Q1 64-bit.

LabVIEW 2023 Q1 Support

VeriStand is compatible with LabVIEW 2023 Q1 64-bit. All custom devices, LabVIEW models, and LabVIEW applications that contain the VeriStand API require this LabVIEW version. The VeriStand API will not install in previous versions of LabVIEW.

LabVIEW 2023 Q1 64-bit supports CompactRIO controllers and NI R Series modules. Custom devices and LabVIEW FPGA development can use LabVIEW 64-bit.

External Mode with XCP Communication

Enable external mode with XCP communication when building a MathWorks Simulink model to monitor signals and tune parameters from the Simulink environment. XCP provides additional capabilities such as viewing signals within referenced models. For more information, refer to the VeriStand Model Generation Support documentation on GitHub.

Terminal Specification for DAQmx Counter Operations

Use System Explorer or the System Definition .NET API to specify the following terminals for DAQmx counter tasks.

• Terminal for counter I/O tasks.
• A/B/Z terminal for position measurement tasks.

Specifying these terminals allows modules to use all counters through non-default PFI lines. For more information, refer to documentation for your module.

HDL Coder Support for PXIe R-series Kintex-7 and Simscape Models

HDL Coder Support Package for NI FPGA Hardware supports the following:

• PXIe R-series Kintex-7 modules ─ Use the support package to remain within HDL Coder while generating a bitfile from a Simulink model for compatible NI FPGA hardware.
• Simscape models.