Block Diagram

Figure 5. PXIe-7903 Block Diagram

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Table 4. MGT Resources
Connector Mini-SAS zHD Connector Lane CLIP Signal Name Common Physical Resource Channel Physical Resource
Port 0 0 MgtPortRx_p/n(0), MgtPortTx_p/n(0) GTYE4_COMMON_X0Y0 GTYE4_CHANNEL_X0Y1
1 MgtPortRx_p/n(1), MgtPortTx_p/n(1) GTYE4_CHANNEL_X0Y0
2 MgtPortRx_p/n(2), MgtPortTx_p/n(2) GTYE4_CHANNEL_X0Y2
3 MgtPortRx_p/n(3), MgtPortTx_p/n(3) GTYE4_CHANNEL_X0Y3
Port 1 0 MgtPortRx_p/n(4), MgtPortTx_p/n(4) GTYE4_COMMON_X0Y1 GTYE4_CHANNEL_X0Y5
1 MgtPortRx_p/n(5), MgtPortTx_p/n(5) GTYE4_CHANNEL_X0Y4
2 MgtPortRx_p/n(6), MgtPortTx_p/n(6) GTYE4_CHANNEL_X0Y6
3 MgtPortRx_p/n(7), MgtPortTx_p/n(7) GTYE4_CHANNEL_X0Y7
Port 2 0 MgtPortRx_p/n(8), MgtPortTx_p/n(8) GTYE4_COMMON_X0Y2 GTYE4_CHANNEL_X0Y9
1 MgtPortRx_p/n(9), MgtPortTx_p/n(9) GTYE4_CHANNEL_X0Y8
2 MgtPortRx_p/n(10), MgtPortTx_p/n(10) GTYE4_CHANNEL_X0Y10
3 MgtPortRx_p/n(11), MgtPortTx_p/n(11) GTYE4_CHANNEL_X0Y11
Port 3 0 MgtPortRx_p/n(12), MgtPortTx_p/n(12) GTYE4_COMMON_X0Y3 GTYE4_CHANNEL_X0Y13
1 MgtPortRx_p/n(13), MgtPortTx_p/n(13) GTYE4_CHANNEL_X0Y12
2 MgtPortRx_p/n(14), MgtPortTx_p/n(14) GTYE4_CHANNEL_X0Y14
3 MgtPortRx_p/n(15), MgtPortTx_p/n(15) GTYE4_CHANNEL_X0Y15
Port 4 0 MgtPortRx_p/n(16), MgtPortTx_p/n(16) GTYE4_COMMON_X1Y4 GTYE4_CHANNEL_X1Y17
1 MgtPortRx_p/n(17), MgtPortTx_p/n(17) GTYE4_CHANNEL_X1Y16
2 MgtPortRx_p/n(18), MgtPortTx_p/n(18) GTYE4_CHANNEL_X1Y18
3 MgtPortRx_p/n(19), MgtPortTx_p/n(19) GTYE4_CHANNEL_X1Y19
Port 5 0 MgtPortRx_p/n(20), MgtPortTx_p/n(20) GTYE4_COMMON_X1Y5 GTYE4_CHANNEL_X1Y21
1 MgtPortRx_p/n(21), MgtPortTx_p/n(21) GTYE4_CHANNEL_X1Y20
2 MgtPortRx_p/n(22), MgtPortTx_p/n(22) GTYE4_CHANNEL_X1Y22
3 MgtPortRx_p/n(23), MgtPortTx_p/n(23) GTYE4_CHANNEL_X1Y23
Port 6 0 MgtPortRx_p/n(24), MgtPortTx_p/n(24) GTYE4_COMMON_X1Y6 GTYE4_CHANNEL_X1Y25
1 MgtPortRx_p/n(25), MgtPortTx_p/n(25) GTYE4_CHANNEL_X1Y24
2 MgtPortRx_p/n(26), MgtPortTx_p/n(26) GTYE4_CHANNEL_X1Y26
3 MgtPortRx_p/n(27), MgtPortTx_p/n(27) GTYE4_CHANNEL_X1Y27
Port 7 0 MgtPortRx_p/n(28), MgtPortTx_p/n(28) GTYE4_COMMON_X1Y7 GTYE4_CHANNEL_X1Y29
1 MgtPortRx_p/n(29), MgtPortTx_p/n(29) GTYE4_CHANNEL_X1Y28
2 MgtPortRx_p/n(30), MgtPortTx_p/n(30) GTYE4_CHANNEL_X1Y30
3 MgtPortRx_p/n(31), MgtPortTx_p/n(31) GTYE4_CHANNEL_X1Y31
Port 8 0 MgtPortRx_p/n(32), MgtPortTx_p/n(32) GTYE4_COMMON_X0Y4 GTYE4_CHANNEL_X0Y17
1 MgtPortRx_p/n(33), MgtPortTx_p/n(33) GTYE4_CHANNEL_X0Y16
2 MgtPortRx_p/n(34), MgtPortTx_p/n(34) GTYE4_CHANNEL_X0Y18
3 MgtPortRx_p/n(35), MgtPortTx_p/n(35) GTYE4_CHANNEL_X0Y19
Port 9 0 MgtPortRx_p/n(36), MgtPortTx_p/n(36) GTYE4_COMMON_X0Y5 GTYE4_CHANNEL_X0Y21
1 MgtPortRx_p/n(37), MgtPortTx_p/n(37) GTYE4_CHANNEL_X0Y20
2 MgtPortRx_p/n(38), MgtPortTx_p/n(38) GTYE4_CHANNEL_X0Y22
3 MgtPortRx_p/n(39), MgtPortTx_p/n(39) GTYE4_CHANNEL_X0Y23
Port 10 0 MgtPortRx_p/n(40), MgtPortTx_p/n(40) GTYE4_COMMON_X0Y6 GTYE4_CHANNEL_X0Y25
1 MgtPortRx_p/n(41), MgtPortTx_p/n(41) GTYE4_CHANNEL_X0Y24
2 MgtPortRx_p/n(42), MgtPortTx_p/n(42) GTYE4_CHANNEL_X0Y26
3 MgtPortRx_p/n(43), MgtPortTx_p/n(43) GTYE4_CHANNEL_X0Y27
Port 11 0 MgtPortRx_p/n(44), MgtPortTx_p/n(44) GTYE4_COMMON_X0Y7 GTYE4_CHANNEL_X0Y29
1 MgtPortRx_p/n(45), MgtPortTx_p/n(45) GTYE4_CHANNEL_X0Y28
2 MgtPortRx_p/n(46), MgtPortTx_p/n(46) GTYE4_CHANNEL_X0Y30
3 MgtPortRx_p/n(47), MgtPortTx_p/n(47) GTYE4_CHANNEL_X0Y31

Each reference clock is driven by one of the two clocking integrated circuits (ICs), listed in the following table. Each clocking IC can generate two independent frequencies, for a total of four possible frequencies across all ports.

Note MgtRefClk_p/n are connected to REFCLK0 of each respective quad.
Table 5. MGT Clocking
Connector CLIP Signal Name Common Physical Resource User Clock Index Clocking IC
CLK OUT N/A N/A 0 2
Port 0 MgtRefClk_p/n(0) GTYE4_COMMON_X0Y0 1[1]1 User Clock 1 controls both MgtRefClk_p/n(0) and MgtRefClk_p/n(1). These clocks cannot be independently configured. 1
Port 1 MgtRefClk_p/n(1) GTYE4_COMMON_X0Y1
Port 2 MgtRefClk_p/n(2) GTYE4_COMMON_X0Y2 2[2]2 User Clock 2 controls both MgtRefClk_p/n(2) and MgtRefClk_p/n(3). These clocks cannot be independently configured.
Port 3 MgtRefClk_p/n(3) GTYE4_COMMON_X0Y3
Port 4 MgtRefClk_p/n(4) GTYE4_COMMON_X1Y4 3 2
Port 5 MgtRefClk_p/n(5) GTYE4_COMMON_X1Y5 4
Port 6 MgtRefClk_p/n(6) GTYE4_COMMON_X16 5
Port 7 MgtRefClk_p/n(7) GTYE4_COMMON_X1Y7 6
Port 8 MgtRefClk_p/n(8) GTYE4_COMMON_X0Y4 7 1
Port 9 MgtRefClk_p/n(9) GTYE4_COMMON_X0Y5 8
Port 10 MgtRefClk_p/n(10) GTYE4_COMMON_X0Y6 9
Port 11 MgtRefClk_p/n(11) GTYE4_COMMON_X0Y7 10

1 User Clock 1 controls both MgtRefClk_p/n(0) and MgtRefClk_p/n(1). These clocks cannot be independently configured.

2 User Clock 2 controls both MgtRefClk_p/n(2) and MgtRefClk_p/n(3). These clocks cannot be independently configured.