PXIe-6594 Front Panel and Pinouts

Use the pinout to connect to terminals on the PXIe-6594.

Figure 3. PXIe-6594 Front Panel


Table 2. Front Panel Connectors
Connector Connector Type Function
DIO Molex Nano-Pitch DIO connector Multi-signal digital I/O connector that provides access to FPGA multi-gigabit transceivers (MGTs) and general-purpose LVCMOS signals
PORT 0, PORT 1 QSFP, SFF-8436 compliant High-speed serial interfacing ports
CLK OUT Standard SMA female connector Output for exported clock
REF/CLK IN Standard SMA female connector Input for an external Reference Clock
Figure 4. DIO Connector Pinout


Table 3. DIO Connector Descriptions
Signal Type Direction
MGT Tx± <0..3> Xilinx UltraScale+ GTY Output
MGT Rx± <0..3> Xilinx UltraScale+ GTY Input
DIO <0..7> Single-ended Bidirectional
5.0 V DC Output
GND Ground —
Figure 5. PORT 0, PORT 1 Connector Pinout


Table 4. PORT 0, PORT 1 Connector Descriptions
Symbol Signal Name
Txn Transmitter Inverted Data Input
Txp Transmitter Non-Inverted Data Input
Rxn Receiver Inverted Data Output
Rxp Receiver Non-Inverted Data Output
SCL 2-Wire Serial Interface Clock
SDA 2-Wire Serial Interface Data
ModPrsL Module Present
ModSelL Module Select
ResetL Module Reset
IntL Interrupt
LPMode Low Power Mode
Vcc Rx +3.3 V Power Supply Receiver
Vcc Tx +3.3 V Power Supply Transmitter
Vcc1 +3.3 V Power Supply
GND Ground