Component-Level Intellectual Property (CLIP)

The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.

  • User-defined CLIP—Allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI.
  • Socketed CLIP—Provides the same IP integration of the user-defined CLIP, but it also allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface.

    • The PXIe-6594 ships with socketed CLIP items that add module I/O to the LabVIEW project.

    Refer to Configuring Your Adapter Module Using LabVIEW FPGA in the FlexRIO User Manual for more information about CLIP.