PXIe-1081 System Reference Clocks

Learn how the chassis generates and distributes reference clocks. Understand the priority of external sources and the default behavior of synchronization outputs.

Reference Clock Architecture

The chassis generates the following PXI timing signals from a common 100 MHz voltage-controlled crystal oscillator (VCXO):
  • PXIe_CLK100
  • PXI_CLK10
  • PXIe_SYNC100

The system derives PXIe_CLK100 directly from the oscillator, produces PXI_CLK10 by dividing the VCXO frequency by 10, and synthesizes PXIe_SYNC100 to maintain a defined phase relationship with PXIe_CLK100. This architecture ensures that PXI_CLK10 and PXIe_CLK100 remain coherent and protected from glitches when switching between clock sources. The system distributes all three signals through low-skew fanout buffers.

Figure 2. PXIe-1081 Reference Clock Architecture

Block diagram showing the PXIe-1081 reference clock distribution. A VCXO DAC feeds a 100 MHz VCXO, which connects to a CLK100 Fanout Buffer. This buffer distributes the 100 MHz clock to PXIe slots and to a SYNC100 CLK10 Synthesis block. The synthesis block outputs to both a SYNC100 Fanout Buffer and a CLK10 Fanout Buffer, which distribute SYNC100 and CLK10 signals to PXIe slots.

Default Clock Synchronization Behavior

The chassis maintains the timing relationship between PXIe_CLK100, PXI_CLK10, and PXIe_SYNC100 across all slots. All three signals originate from the same 100 MHz voltage-controlled crystal oscillator (VCXO), ensuring consistent synchronization throughout the system. The clock architecture avoids glitches and phase shifts during transitions between internal and external clock sources.

Figure 3. PXIe-1081 System Reference Clock Default Behavior

Timing diagram showing three clock signals: PXIe_CLK100 with high-frequency cycles, PXI_CLK10 with lower-frequency cycles, and PXIe_SYNC100 with periodic transitions. The time axis spans from 0 to 9, repeating across the diagram. The signals illustrate default synchronization behavior in PXIe systems.