DAQ_Digital Clock Generation Library VIs initialize, configure, generate, and close user-configurable terminals using counters. This library is applicable for digital I/O channels and modules that support timing output signals with PFI channels or other connections.

  1. Use the DAQ_Digital Clk Gen Initialize VI to initialize hardware and create a DAQmx Task for dynamic digital clock generation.
  2. Specify the physical channel input to use for the counter. Only one counter can be used for a task. Use separate tasks for each counter if multiple counters are required.
    Note TestScale devices do not support frequency generation because the generation time and duty cycle cannot be controlled. Refer to Using the Frequency Generator in the TestScale Features manual for details.
  3. Provide the output terminal on which to generate the signal. Refer to the NI-DAQmx Device Terminals Help table. To access the table in NI MAX, select your device and right-click Device Pinout. Use the table to view the default PFI terminals of each counter for your device.
  4. If necessary, configure PFI lines.
    Note For the TestScale TS-15050 module only, P0.DIO<0:7> channels map to PFI<0:7> terminals. Refer to the TS-15050 Specifications for more information.
  5. Pass the digital clock generation DAQmx Task to the DAQ_Digital Clk Gen Configure and Measure VI.
  6. Configure the DAQ_Digital Clk Gen Configure and Measure VI.
    • Frequency (Hz)—Specifies the frequency to generate pulses.
    • Duty cycle (%)—Specifies the duty cycle to generate pulses.
    • Generation Time—Specifies the time for the generation of the digital clock signal. Set generation times as an integral multiple of the time period (1/Frequency (Hz)) to generate complete cycles.
    • Actual Pulse Settings—Returns the frequency, duty cycle and generation time of the generated digital signal from the instrument.
  7. Wire the updated digital clock generation task from DAQmx Task Out.
  8. Close the digital clock generation task using DAQ_Digital Clk Gen Close VI.
Figure 32. Connection Block Diagram