IMAQ FPGA FIFO to Pixel Bus VI

Source Image FIFO refers to the FIFO that contains the image pixels to process. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the host processor to the target FPGA.

Image Size specifies the image width and height in pixels. These values are used to determine when to assert the EOL and EOI flags in the Pixel Bus Out cluster. If either the Width or Height value is 0, the Output Valid terminal returns FALSE during that cycle. If this VI will be used with a Host to Target DMA FIFO, creating a front panel control for this input on the top-level FPGA VI will allow the IMAQ FPGA Configure Image Transfer to Target VI on the host to set this value.

	Width is the width of the image in pixels.
	Height is the height of the image in pixels.

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

	Pixel Data is the value of the pixel.
	DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).
	EOL End of line. When TRUE, indicates that the end of the line has been reached.
	EOI End of image. When TRUE, indicates that the end of the image has been reached.
	Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

Source FIFO Status returns the status of the FIFO designated by the Source Image FIFO input. If this VI will be used with a Host to Target DMA FIFO, creating a front panel indicator for this output on the top-level FPGA VI will allow the IMAQ FPGA Wait for Image Transfer Complete VI on the host to get this value in order to determine when the FIFO is empty.

Number of Elements to Read is the current depth of the FIFO. When this value reaches 0, the FIFO is empty.

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

Source Image FIFO refers to the FIFO that contains the image pixels to process. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the host processor to the target FPGA.

Image Size specifies the image width and height in pixels. These values are used to determine when to assert the EOL and EOI flags in the Pixel Bus Out cluster. If either the Width or Height value is 0, the Output Valid terminal returns FALSE during that cycle. If this VI will be used with a Host to Target DMA FIFO, creating a front panel control for this input on the top-level FPGA VI will allow the IMAQ FPGA Configure Image Transfer to Target VI on the host to set this value.

	Width is the width of the image in pixels.
	Height is the height of the image in pixels.

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

	Pixel Data is the value of the pixel.
	DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).
	EOL End of line. When TRUE, indicates that the end of the line has been reached.
	EOI End of image. When TRUE, indicates that the end of the image has been reached.
	Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

Source FIFO Status returns the status of the FIFO designated by the Source Image FIFO input. If this VI will be used with a Host to Target DMA FIFO, creating a front panel indicator for this output on the top-level FPGA VI will allow the IMAQ FPGA Wait for Image Transfer Complete VI on the host to get this value in order to determine when the FIFO is empty.

Number of Elements to Read is the current depth of the FIFO. When this value reaches 0, the FIFO is empty.

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

Source Image FIFO refers to the FIFO that contains the image pixels to process. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the host processor to the target FPGA.

Image Size specifies the image width and height in pixels. These values are used to determine when to assert the EOL and EOI flags in the Pixel Bus Out cluster. If either the Width or Height value is 0, the Output Valid terminal returns FALSE during that cycle. If this VI will be used with a Host to Target DMA FIFO, creating a front panel control for this input on the top-level FPGA VI will allow the IMAQ FPGA Configure Image Transfer to Target VI on the host to set this value.

	Width is the width of the image in pixels.
	Height is the height of the image in pixels.

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

	Pixel Data is the value of the pixel.
	DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).
	EOL End of line. When TRUE, indicates that the end of the line has been reached.
	EOI End of image. When TRUE, indicates that the end of the image has been reached.
	Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

Source FIFO Status returns the status of the FIFO designated by the Source Image FIFO input. If this VI will be used with a Host to Target DMA FIFO, creating a front panel indicator for this output on the top-level FPGA VI will allow the IMAQ FPGA Wait for Image Transfer Complete VI on the host to get this value in order to determine when the FIFO is empty.

Number of Elements to Read is the current depth of the FIFO. When this value reaches 0, the FIFO is empty.

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

Source Image FIFO refers to the FIFO that contains the image pixels to process. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the host processor to the target FPGA.

Image Size specifies the image width and height in pixels. These values are used to determine when to assert the EOL and EOI flags in the Pixel Bus Out cluster. If either the Width or Height value is 0, the Output Valid terminal returns FALSE during that cycle. If this VI will be used with a Host to Target DMA FIFO, creating a front panel control for this input on the top-level FPGA VI will allow the IMAQ FPGA Configure Image Transfer to Target VI on the host to set this value.

	Width is the width of the image in pixels.
	Height is the height of the image in pixels.

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

	Pixel Data is the value of the pixel.
	DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).
	EOL End of line. When TRUE, indicates that the end of the line has been reached.
	EOI End of image. When TRUE, indicates that the end of the image has been reached.
	Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

Source FIFO Status returns the status of the FIFO designated by the Source Image FIFO input. If this VI will be used with a Host to Target DMA FIFO, creating a front panel indicator for this output on the top-level FPGA VI will allow the IMAQ FPGA Wait for Image Transfer Complete VI on the host to get this value in order to determine when the FIFO is empty.

Number of Elements to Read is the current depth of the FIFO. When this value reaches 0, the FIFO is empty.

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

Source Image FIFO refers to the FIFO that contains the image pixels to process. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the host processor to the target FPGA.

Image Size specifies the image width and height in pixels. These values are used to determine when to assert the EOL and EOI flags in the Pixel Bus Out cluster. If either the Width or Height value is 0, the Output Valid terminal returns FALSE during that cycle. If this VI will be used with a Host to Target DMA FIFO, creating a front panel control for this input on the top-level FPGA VI will allow the IMAQ FPGA Configure Image Transfer to Target VI on the host to set this value.

	Width is the width of the image in pixels.
	Height is the height of the image in pixels.

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

	Pixel Data is the value of the pixel. A is the value of the alpha plane. R/H is the red or hue value of the first color plane, depending on the color mode. G/S is the green or saturation value of the second color plane, depending on the color mode. B/L is the blue or luminance value of the third color plane, depending on the color mode.
	DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).
	EOL End of line. When TRUE, indicates that the end of the line has been reached.
	EOI End of image. When TRUE, indicates that the end of the image has been reached.
	Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

Source FIFO Status returns the status of the FIFO designated by the Source Image FIFO input. If this VI will be used with a Host to Target DMA FIFO, creating a front panel indicator for this output on the top-level FPGA VI will allow the IMAQ FPGA Wait for Image Transfer Complete VI on the host to get this value in order to determine when the FIFO is empty.

Number of Elements to Read is the current depth of the FIFO. When this value reaches 0, the FIFO is empty.

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

Source Image FIFO refers to the FIFO that contains the image pixels to process. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the host processor to the target FPGA.

Image Size specifies the image width and height in pixels. These values are used to determine when to assert the EOL and EOI flags in the Pixel Bus Out cluster. If either the Width or Height value is 0, the Output Valid terminal returns FALSE during that cycle. If this VI will be used with a Host to Target DMA FIFO, creating a front panel control for this input on the top-level FPGA VI will allow the IMAQ FPGA Configure Image Transfer to Target VI on the host to set this value.

	Width is the width of the image in pixels.
	Height is the height of the image in pixels.

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

	Pixel Data is the value of the pixel. A is the value of the alpha plane. R/H is the red or hue value of the first color plane, depending on the color mode. G/S is the green or saturation value of the second color plane, depending on the color mode. B/L is the blue or luminance value of the third color plane, depending on the color mode.
	DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).
	EOL End of line. When TRUE, indicates that the end of the line has been reached.
	EOI End of image. When TRUE, indicates that the end of the image has been reached.
	Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

Source FIFO Status returns the status of the FIFO designated by the Source Image FIFO input. If this VI will be used with a Host to Target DMA FIFO, creating a front panel indicator for this output on the top-level FPGA VI will allow the IMAQ FPGA Wait for Image Transfer Complete VI on the host to get this value in order to determine when the FIFO is empty.

Number of Elements to Read is the current depth of the FIFO. When this value reaches 0, the FIFO is empty.

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

Source Image FIFO refers to the FIFO that contains the image pixels to process. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the host processor to the target FPGA.

Image Size specifies the image width and height in pixels. These values are used to determine when to assert the EOL and EOI flags in the Pixel Bus Out cluster. If either the Width or Height value is 0, the Output Valid terminal returns FALSE during that cycle. If this VI will be used with a Host to Target DMA FIFO, creating a front panel control for this input on the top-level FPGA VI will allow the IMAQ FPGA Configure Image Transfer to Target VI on the host to set this value.

	Width is the width of the image in pixels.
	Height is the height of the image in pixels.

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

	Pixel Data is the value of the pixel. A is the value of the alpha plane. R/H is the red or hue value of the first color plane, depending on the color mode. G/S is the green or saturation value of the second color plane, depending on the color mode. B/L is the blue or luminance value of the third color plane, depending on the color mode.
	DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).
	EOL End of line. When TRUE, indicates that the end of the line has been reached.
	EOI End of image. When TRUE, indicates that the end of the image has been reached.
	Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

Source FIFO Status returns the status of the FIFO designated by the Source Image FIFO input. If this VI will be used with a Host to Target DMA FIFO, creating a front panel indicator for this output on the top-level FPGA VI will allow the IMAQ FPGA Wait for Image Transfer Complete VI on the host to get this value in order to determine when the FIFO is empty.

Number of Elements to Read is the current depth of the FIFO. When this value reaches 0, the FIFO is empty.

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

Source Image FIFO refers to the FIFO that contains the image pixels to process. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the host processor to the target FPGA.

Image Size specifies the image width and height in pixels. These values are used to determine when to assert the EOL and EOI flags in the Pixel Bus Out cluster. If either the Width or Height value is 0, the Output Valid terminal returns FALSE during that cycle. If this VI will be used with a Host to Target DMA FIFO, creating a front panel control for this input on the top-level FPGA VI will allow the IMAQ FPGA Configure Image Transfer to Target VI on the host to set this value.

	Width is the width of the image in pixels.
	Height is the height of the image in pixels.

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

	Pixel Data is the value of the pixel. A is the value of the alpha plane. R/H is the red or hue value of the first color plane, depending on the color mode. G/S is the green or saturation value of the second color plane, depending on the color mode. B/L is the blue or luminance value of the third color plane, depending on the color mode.
	DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).
	EOL End of line. When TRUE, indicates that the end of the line has been reached.
	EOI End of image. When TRUE, indicates that the end of the image has been reached.
	Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

Source FIFO Status returns the status of the FIFO designated by the Source Image FIFO input. If this VI will be used with a Host to Target DMA FIFO, creating a front panel indicator for this output on the top-level FPGA VI will allow the IMAQ FPGA Wait for Image Transfer Complete VI on the host to get this value in order to determine when the FIFO is empty.

Number of Elements to Read is the current depth of the FIFO. When this value reaches 0, the FIFO is empty.

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.