Image Transfer

Reads image pixels out of the specified FIFO and returns a Pixel Bus cluster of the requested type. The Pixel Bus contains the pixel data from the FIFO along with some additional flags that indicate when the pixel data is valid, an end of a line has been reached, or an end of the image has been reached. The Pixel Bus is used to pass image data to all of the other VIs in the NI Vision Development Module for FPGA library. Only one of the DV, EOL, and EOI flags in the Pixel Bus cluster will assert on a given clock cycle. When the last pixel of an image is reached, the Pixel Bus will contain the pixel data and the DV flag will be TRUE and the EOL and EOI flags will be FALSE. The next clock cycle, the EOL flag will be TRUE and the DV and EOI flags will be FALSE. The following clock cycle, the EOI flag will be TRUE and the DV and EOL flags will be FALSE.

Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.