IMAQ FPGA Pixel Bus to FIFO VI
- Updated2023-02-21
- 24 minute(s) read
Requires: NI Vision Development Module
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
The data type of the FIFO must match the fundamental data type of the pixel:
- A U1 or U8 pixel must match a U8 FIFO
- A U16 pixel must match a U16 FIFO
- A U32 pixel must match a RGB32 FIFO or HSL32 FIFO
IMAQ FPGA Pixel Bus to FIFO U1x1
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO U1x8
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO U8x1
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO U8x8
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO U8x16
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
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|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO U8x32
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO U16x1
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO U16x8
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO RGB32x1
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
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|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Pixel Bus to FIFO RGB32x8
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Pixel Bus to FIFO HSL32x1
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Pixel Bus to FIFO HSL32x8
Writes valid Pixel Data in the Pixel Bus cluster to the specified FIFO. If the FIFO is full, the Ready for Input terminal returns FALSE during that cycle.
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Destination Image FIFO refers to the FIFO that will contain the processed image pixel. This FIFO can be any type of FIFO supported by LabVIEW FPGA, but typically this will refer to a DMA FIFO that is transferring image pixels from the target FPGA to the host processor. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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