You can use synchronization clocks to synchronize separate signals coming from the front and back zones of your PXI chassis. Using the niSync Property Node, you can set the synchronization clock for each zone. The synchronization clock can be the backplane clock, a generated DDS clock, a module's oscillator, or a clock originating from the PFI0 or ClkIn front panel connector of your module. You can also use the niSync Property Node to divide down a synchronization clock into a lower frequency.

Dividing a synchronization clock is a good choice for applications where you want one set of triggers to fire more or less frequently than another while still having both sets of triggers synchronized to the same reference clock. You can use a full-speed or divided synchronization clock to perform the following actions:

  • Synchronize the firing of triggers.
  • Export a clock through a PXI_Star or PXIe_DStar line within a single chassis.
  • Export a clock through a PFI or PFI_LVDS line to synchronize multiple chassis, modules, and/or devices with the clock.
  • Use multiple sample clocks that run in different increments but have the same concept of time.
  • Synchronize front panel inputs to a different frequency than the PXI backplane and vice versa.

Refer to the following topics to use synchronization clocks in a program:

  • Setting and Dividing a Synchronization Clock
  • Routing a Synchronization Clock Along a Trigger Line
  • Firing Triggers with a Synchronization Clock