Prerequisites: Setting and Dividing a Synchronization Clock

You can route full-speed or divided synchronization clocks through trigger lines using niSync Connect Trigger Terminals. Using this technique, you can export a DDS clock using a PFI line and send full-speed or divided clocks along routes that are not accessible when you use niSync Connect Clock Terminals alone.
Caution   Routing a clock signal through a PXI_Trig line is not recommended, due to poor clock signal integrity caused by the topology of the PXI_Trig lines. Use PXI_Star, PXIe_DStar, or PFI lines instead.

Complete the following steps to route a synchronization clock along a trigger line:

  1. Place niSync Connect Trigger Terminals.
  2. Wire a constant or control to source and destination.
  3. Select Synchronization Clock (Divided 2) for source. This divides the synchronization clock by the value you set in the Clock Divisor 2 parameter of the niSync Property Node and uses the result as the source for this trigger. You can also select Synchronization Clock (Divided 1) or Synchronization Clock (Full Speed).
  4. Select a destination for niSync Connect Trigger Terminals:
    • Select a PXI_Star line to route the specified clock through the backplane trigger lines of your chassis.
    • Select a front panel terminal (PFI, PFI_LVDS) to route the specified clock through the front zone of your chassis to another PXI chassis, a physically connected module in the same chassis, or an external device.
    • Select PXIe_DStarB to route the specified clock from a system timing module to a peripheral slot.
    • Select PXIe_DStarC to route the specified clock from a peripheral slot to a system timing module.
  5. Place niSync Disconnect Trigger Terminals to free the trigger lines for other applications.
  6. Place niSync Close to end the NI-Sync session.

After completing the preceding steps, the synchronization clock you set using the niSync Property Node is routed to a different location in your chassis using a trigger line.