The following data position settings are available for acquisition and generation channels:

  • Sample clock rising edge—Data is generated/acquired on the rising edge of the clock driving the operation.
  • Sample clock falling edge—Data is generated/acquired on the falling edge of the clock driving the operation.
  • Delay from Sample clock rising edge—Data is generated or acquired at a specified time after the rising edge of the clock driving the operation. The data position delay resolution depends on your device and clock frequency.
    • For PXI-6547/6548 devices, channels are arranged into three different banks for multibank data delay.
    Note NI 656x devices have special considerations for legal delayed data settings for Sample clock frequencies between 25 and 50 MHz.