NI Data Link Test Framework provides several Vivado Export templates to allow you to take advantage of the design features provided by the Vivado Design Suite while making full use of the NI Data Link Test Framework on NI FPGA hardware resources.

Note For more information about the Vivado export process, refer to Exporting FPGA VIs as Vivado Design Suite Projects in the LabVIEW FPGA Module User Manual.
  • dmsc 6594_00 Vivado Export Template—Use this template to develop an I/Q data streaming application (up to 1.25 GS/s) using a PXIe-6594 coprocessor and another supported endpoint.
  • dmsc 7903_00 Vivado Export Template—Use this template to develop an I/Q data streaming application (up to 1.25 GS/s) using a PXIe-7903 coprocessor and another supported endpoint.
  • dmsc 7903_01 Vivado Export Template—Use this template to develop an I/Q data streaming application (up to 2.5 GS/s) using a PXIe-7903 coprocessor and another supported endpoint.
  • dmsc 7903_05 Vivado Export Template—Use this template to develop an I/Q data streaming application (up to 5 GS/s) using a PXIe-7903 coprocessor and another supported endpoint.
  • dmsc 7915_00 Vivado Export Template—Use this template to develop an I/Q data streaming application (up to 1.25 GS/s) using a PXIe-7915 coprocessor and another supported endpoint.

    • Modifying the Templates

    For each FPGA VI, NI Data Link Test Framework provides a build specification that exports the VI as a Vivado Design Suite project.

    Note For more information about exporting an FPGA VI, and designing and compiling an exported project, refer to Exporting FPGA VIs as Vivado Design Suite Projects in the LabVIEW FPGA Module User Manual.

    The templates are provided with example UserRTL VHD files that define the CLIP interfaces—such as clocks, AXI4-Lite, AXI4-Stream interface, and so on—in the form of input and output signals:

    • UserRTL_rx_ip.vhd
    • UserRTL_tx_ip.vhd

    Modify the VHD file for the different connecting signals, clocks, and so on, for your design.

    NI Data Link Test Framework provides the following CLIPs with the project that correspond to the VHD files:

    • rxClip
    • txClip

    As you modify UserRTL_tx_ip.vhd or UserRTL_rx_ip.vhd, you must update the corresponding txClip or rxClip. Modify the CLIP in one of the following ways:

    • In LabVIEW, create a new CLIP by right-clicking the FPGA Target and selecting New » Component Level-IP and following the steps.
    • Right-click an existing txClip or rxClip, select Properties, and follow the subsequent steps.

    The process creates or updates the XML file corresponding to the VHD file.

    Note If you create a new VHD file, you must first add it as CLIP declaration, as described in Adding Component-Level IP to a Project in the LabVIEW FPGA Module User Manual.

    Vivado Export Template VIs

    All Vivado Export template projects provide the following template VIs that interface between LabVIEW FPGA and external IP through Component Level IP (CLIP) nodes.