Use this template as a starting point for applications where RF data is acquired on a VST and streamed to a coprocessor for processing of the acquired I/Q data.

The Receive template defines a starting point intended for adaptation to your specific use case. The interface options described below should be modified depending on the specific IP that is intended to be implemented with the rxClip.

The Receive VI operates as follows:

  1. Defines a 256-bit AXI4-Stream interface as an input for the rxClip. This interface is connected to the Read Data Stream VI method of the DLsc FPGA API and can be used to stream data from a compatible VST and coprocessor to the rxClip.
  2. Defines a 256-bit AXI4-Stream interface as an output for the rxClip. This interface is connected to a Target-to-Host DMA and can be used to write data from the rxClip to the host.
  3. Defines a 32-bit, 512 element AXI4-Lite Interface for the rxClip. This interface is made available to the rxClip and can be used to configure registers from the host.
  4. Defines an FPGA I/O Node interface for the rxClip. This interface is connected to front panel controls and indicator on the block diagram and can be used to provide control/status of the specific net within the rxClip.
  5. Defines multiple Debug interfaces that demonstrate how multiple interfaces can be added for activities, such as debugging for when you may want to send other data back to the Host Application.