Transmit DMA VI
- Updated2025-10-07
- 1 minute(s) read
Use this template as a starting point for IP validation on a single coprocessor.
The Transmit DMA template defines a starting point intended for adaptation to your specific use case. The interface options described below should be modified depending on the specific IP that is intended to be implemented with the txClip.
The Transmit DMA VI operates as follows:
- Defines a 256-bit AXI4-Stream interface as an input for the txClip. This interface is connected to a Host-to-Target DMA and can be used to write data from the host application for use within the txClip.
- Defines a 512-bit AXI4-Stream interface as an output for the txClip. This interface is connected to a Target-to-Host DMA and can be used to write data from the txClip to the host application.
- Defines a 32-bit, 512 element AXI4-Lite Interface for the txClip. This interface is made available to the txClip and can be used to configure registers from the host.
- Defines an FPGA I/O Node interface for the txClip. This interface is connected to front panel controls and indicator on the block diagram and can be used to provide control and the status of the specific net within the txClip.