Computes the hyperbolic sine and cosine of x. The value of x must be in the range [–1, 1).

This function supports only scalar values of the fixed-point data type.


icon

Dialog Box Options

Option Description
General

Specifies general information about this function.

  • Fixed-Point Configuration—

    Specifies the encodings, word lengths, and integer word lengths of the input and output terminals of this function. The configurations you specify determine the value range of the terminals.

    • x Type—

      Specifies the fixed-point configuration of the x input terminal.

      If you wire a fixed-point data type to this terminal and that data type follows the rules for this terminal, LabVIEW dims this section and uses information from the wire. If you wire a fixed-point data type to this terminal that does not follow the rules, LabVIEW breaks the wire.

      • Signed—Specifies that this terminal is signed.
      • Unsigned—Specifies that this terminal is unsigned.
      • Word length—Specifies the word length of this terminal.
      • Integer word length—Specifies the integer word length of this terminal. If the encoding is Signed, the maximum value is 1 bit. If the encoding is Unsigned, the maximum value is 0 bits.
    • sinh(x) Type—

      Specifies the fixed-point configuration of the sinh(x) output terminal.

      • Signed—Specifies that this terminal is signed. sinh(x) can be either positive or negative, so LabVIEW sets the encoding to Signed and dims this option.
      • Unsigned—Specifies that this terminal is unsigned. sinh(x) can be either positive or negative, so LabVIEW sets the encoding to Signed and dims this option.
      • Word length—Specifies the word length of this terminal. The value must be between 4 and 64 bits.

        LabVIEW adjusts the word length of the cosh(x) output terminal to use one fewer bit than the word length of the sinh(x) output terminal.

      • Integer word length—Specifies the integer word length of this terminal. LabVIEW sets this value to 2 bits and dims this option.
    • cosh(x) Type—

      Specifies the fixed-point configuration of the cosh(x) output terminal.

      • Signed—Specifies that this terminal is signed. cosh(x) always is positive, so LabVIEW sets the encoding to Unsigned and dims this option.
      • Unsigned—Specifies that this terminal is unsigned. cosh(x) always is positive, so LabVIEW sets the encoding to Unsigned and dims this option.
      • Word length—Specifies the word length of this terminal. The value must be between 3 and 63 bits.

        LabVIEW adjusts the word length of the sinh(x) output terminal to use one more bit than the word length of the cosh(x) output terminal.

      • Integer word length—Specifies the integer word length of this terminal. LabVIEW sets this value to 1 bit and dims this option.
    • Rounding mode—

      Specifies how this function rounds the output data if rounding is necessary. You can choose Truncate (default), Round Half-Up, or Round Half-Even. If rounding occurs, the option you choose might affect the amount of resources this function requires.

  • Execution Mode—

    Specifies how this function executes.

    • Outside single-cycle Timed Loop—

      Configures this Express VI to execute outside a single-cycle Timed Loop.

      If you select this option and place this Express VI inside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

    • Inside single-cycle Timed Loop—

      Configures this Express VI to execute inside a single-cycle Timed Loop.

      If you select this option and place this Express VI outside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

    • Throughput—

      Specifies the minimum number of cycles between two successive values of valid input data. Entering a low value in this control results in a high throughput rate. The maximum value of Throughput depends on the Word length of the output terminal. This option is available only if you select Inside single-cycle Timed Loop.

      If you select Outside single-cycle Timed Loop, this function returns a valid result on every call to the function. Therefore, the Throughput control displays 1 call / sample. The Configuration Feedback indicator displays the number of clock cycles this function takes to return a valid result.

  • Registers—

    Specifies whether to add internal registers for function inputs and/or outputs. These registers will be placed outside of any embedded resources, such as block multipliers or DSP48E slices. This section is available only if you select Inside single-cycle Timed Loop.

    Note Adding registers can reduce the length of the combinatorial path, which can prevent compilation errors that result from a long combinatorial path. However, adding registers also increases the latency of this function, which means this function takes additional clock cycles to return a valid result.
    • Register inputs—Adds internal registers after the inputs to this function. Selecting this option increases the latency of the function by one cycle.
    • Register outputs—Adds internal registers before the outputs of this function. Selecting this option increases the latency of the function by one cycle.
CORDIC Details

Specifies options for the COordinate Rotation DIgital Computer (CORDIC) algorithm this function uses.

  • Precision—

    Specifies options about the precision of the result(s) this function returns.

    • Number of internal iterations—Specifies the number of cycles this function takes to return a valid result without considering input/output registers.
      • Adapt to configuration—Specifies whether LabVIEW automatically determines the number of internal iterations based on the options you specify on the General page. By default, this checkbox contains a checkmark.
      • Value—Specifies the number of cycles this function takes to return a valid result without considering input/output registers. By default, LabVIEW dims this control and automatically determines this value based on the options you specify on the General page.

        To enable this control, remove the checkmark from the Adapt to configuration checkbox. Increasing the number of internal iterations increases both the precision of the result and the latency of this function.

    • Internal word length—Specifies the word length of internal calculations.
      • Adapt to configuration—Specifies whether LabVIEW automatically determines the value of the internal word length based on the options you specify on the General page and the Value of the Number of internal iterations. By default, this checkbox contains a checkmark.
      • Value—Specifies the word length of internal calculations. By default, LabVIEW dims this control and automatically determines this value based on the options you specify on the General page and the Value of the Number of internal iterations.

        To enable this control, remove the checkmark from the Adapt to configuration checkbox. Increasing the internal word length increases the precision of the output, the amount of FPGA resources this function requires, and the length of the combinatorial path.
Configuration Feedback

Displays information about how this function executes. This information is based on the configuration options you specify.

Inputs/Outputs

  • cunkn.png x —

    Specifies the input to this function. x must be in the range [–1, 1].

  • input valid —

    Specifies whether the next data point has arrived for processing. Wire output valid of an upstream node to input valid to transfer data from the upstream node to this Express VI.

    To display this handshaking terminal, select Inside single-cycle Timed Loop in the configuration dialog box.

  • ready for output —

    Specifies whether downstream nodes are ready for this Express VI to return a new value. The default is TRUE. Use a Feedback Node to wire ready for input of a downstream node to ready for output of the current node.

    Note If ready for output is FALSE during a given cycle, output valid returns FALSE during that cycle.

    To display ready for output, select Inside single-cycle Timed Loop in the configuration dialog box.

  • iunkn.png sinh(x) —

    Returns the hyperbolic sine of x.

  • iunkn.png cosh(x) —

    Returns the hyperbolic cosine of x.

  • output valid —

    Returns TRUE if this Express VI has computed a result that downstream nodes can use. Use output valid for handshaking with other FPGA VIs and functions.

    To display output valid, select Inside single-cycle Timed Loop in the configuration dialog box.

  • ready for input —

    Returns TRUE if this Express VI is ready to accept new input data. Use a Feedback Node to wire ready for input to ready for output of an upstream node.

    Note If ready for input returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this Express VI during the following cycle. LabVIEW discards this data even if input valid is TRUE during the following cycle.

    To display ready for input, select Inside single-cycle Timed Loop in the configuration dialog box.

    • Computing sinh(x) and cosh(x) When x is Outside the Valid Range

    x must be in the range [–1, 1). To compute sinh(x) and cosh(x) when x is outside this range, find an integer q and a real number r, where r is in the range [0, ln(2)), such that x = q × ln(2) + r. You then can make the following computations:

    • 2^(q – 1)[cosh(r) + sinh(r) – 2^(–2q)(cosh(r) – sinh(r))], which is equivalent to sinh(x).
    • 2^(q – 1)[cosh(r) + sinh(r) + 2^(–2q)(cosh(r) – sinh(r))], which is equivalent to cosh(x).

    Because r is in the valid range of [–1, 1), you can use this function to compute sinh(r) and cosh(r).

    Input Terminal Coercion

    The CORDIC algorithm represents x internally as a fixed-point number with a 1-bit integer word length. The word length of x must be less than or equal to 64 bits, which means the fractional word length must be less than or equal to 63 bits. If you wire a value to x that has a fractional word length greater than 63 bits, this function rounds off the lower bits to achieve a fractional word length of 63 bits. For example, if you wire a fixed-point data type with a configuration of <+/–,60,–5> to x, this function coerces the configuration to be <+/–,58,–5>.

    If you wire a fixed-point data type to x with a fractional word length greater than 63 bits and an integer word length less than –62 bits, this function coerces the configuration to be <+/–,1,–62> if the data type is signed. If the data type is unsigned, the coerced configuration is <+,1,–62>.