Writes channel configuration data to the I/O items. Use this node with multiplexed analog input devices where the configuration for a channel transfers from the FPGA to the target I/O on each clock pulse. If the channel configuration does not update with each sample pulse, the previously written configuration transfers again, and the device will continue to acquire from the same channel with the same configuration.


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Inputs/Outputs

  • cerrcodeclst.png error in —

    error in describes error conditions that occur before this node runs. This input provides standard error in functionality.

  • FPGA I/O In —

    FPGA I/O In is an optional input that allows you to specify the FPGA I/O item to read or write using an FPGA I/O control or constant. To use an FPGA I/O control as a connector pane input, the FPGA VI must be configured for reentrant execution.

  • cpoly.png I/O Item —

    I/O Item is the configuration data written to the selected I/O item. The data type and the function of I/O Item vary depending on the hardware.

  • cpoly.png Timeout —

    specifies the maximum time, in number of clock ticks, that the function will wait to write channel configuration data. A value of –1 prevents the function from timing out, so the function completes execution only when it writes all data. If Timeout is 0 and this function cannot write data immediately, a timeout occurs. If a timeout occurs, the previous configuration does not change.

  • Input Valid —

    Input Valid specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

  • ierrcodeclst.png error out —

    error out contains error information. This output provides standard error out functionality.

  • ipoly.png Timed Out —

    returns TRUE if this function times out. If Timed Out is TRUE, this function did not write data to any I/O items.

  • FPGA I/O Out —

    FPGA I/O Out returns the FPGA I/O In.

  • Ready for Input —

    Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

    Note If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

    To display this terminal, right-click the function and select Inside single-cycle Timed Loop from the shortcut menu.

    • The following connector pane displays the parameters that appear when this function is outside a single-cycle Timed Loop.

    Note Not all targets support the User-Controlled I/O Sampling functions.

    This function does not wait for the data to transfer to the I/O items, but only posts the data. This posted data transfers immediately to the I/O item until the I/O item is primed. Once the I/O item is primed, posted data transfers from the FPGA to the I/O item only on each sample pulse the Generate I/O Sample Pulse Method function generates. You must prime the I/O item with data before the Generate I/O Sample Pulse Method function runs or the sample pulse is gated.

    All references to the same I/O item use the same buffer, even if different Configure I/O Method functions reference the I/O item. Functions that write data always wait for the existing data in the buffer to be read and will not overwrite buffer data. When the Generate I/O Sample Pulse Method function executes, the oldest data in the buffer is read. If the buffer is empty when the Generate I/O Sample Pulse Method function executes, the buffer regenerates using stale data. If multiple I/O items are present in the same node, the write occurs only if each I/O item has space available. Otherwise, this function reports a timeout.

    Single-Cycle Timed Loop Details

    This node is supported inside and outside the single-cycle Timed Loop if the target supports it. Right-click the function and select Execution Mode»Outside single-cycle Timed Loop or Inside single-cycle Timed Loop to specify where the function executes.

    Error Handling Details

    You can use the error terminals to place this node in the data flow of the VI as well as to ensure the data you receive is valid. FPGA targets might report errors differently. Refer to the specific FPGA target hardware documentation for information about how specific FPGA targets report errors.