Use the Pattern Detect page to enable, disable, and configure pattern detection. Refer to the following sections of the Virtex-5 FPGA XtremeDSP Design Considerations User Guide or the Virtex-6 FPGA DSP48E1 Slice User Guide, available on the Xilinx Web site at www.xilinx.com, for information about pattern detection:

  • "Pattern Detect Logic"
  • "PATTERNDETECT and PATTERNBDETECT Port Logic"
  • "Pattern Detect Applications" (Virtex-5 FPGA XtremeDSP Design Considerations User Guide only) . This section also provides information about the VHDL generics and options in the table in the following section.

VHDL Equivalent of LabVIEW Options

To view the VHDL equivalent of a configuration, click the VHDL Instantiation tab. Refer to Table 1-3 in either the Virtex-5 FPGA XtremeDSP Design Considerations User Guide or the Virtex-6 FPGA DSP48E1 Slice User Guide, available on the Xilinx Web site at www.xilinx.com, for information about specific attributes. The following table shows the attributes that correspond to each option in LabVIEW.

LabVIEW Option Attribute to Reference in Table 1-3
DSP48E DSP48E1
USE_PATTERN_DETECT
SEL_PATTERN, PATTERN
SEL_ROUNDING_MASK, SEL_MASK, MASK SEL_MASK, MASK

AUTORESET_PATTERN_DETECT, AUTORESET_PATTERN_DETECT_OPTINV AUTORESET_PATDET