The DSP48E or DSP48E1 schematic at the bottom of the configuration dialog box shows the internal combinatorial path of the function. If this combinatorial path is too long, the function cannot compile at the clock rate you specify, and LabVIEW returns errors when you attempt to compile the FPGA VI.

You can avoid these errors by adding internal registers to the function. Adding registers increases the chances that a function can compile at a specified clock rate. However, adding registers also increases the latency of a DSP48E function and might unbalance the latencies of internal data paths relative to one another. Depending on how you are using the function, this imbalance might be acceptable, but you should be aware of the latencies of the internal data paths to ensure the function executes the way you want.

Use the Registers page of the configuration dialog box to add and configure internal registers in a DSP48E slice. Notice that as you add and configure registers, corresponding green boxes light up in the schematic at the bottom of the dialog box. The data paths also might change.

Enabling and Resetting Registers

Each register has a corresponding enable and reset terminal. By default, LabVIEW sets reset terminals to FALSE and enable terminals to TRUE while hiding all terminals from the block diagram. If these settings are acceptable, you do not need to change any settings.

For detailed control over enable and reset operations, use the Enable and Reset pages to specify which enable and reset terminals LabVIEW shows on the block diagram. At the top of each page is a pull-down menu of options you can choose from, as the following illustration shows:

These options have the following effects on registers you have added:

• Hide All Signals—Specifies that LabVIEW does not show any enable or reset terminals on the block diagram. In this situation, LabVIEW applies the default behavior as described above.
• Use a Single Terminal for All Registers—Specifies that LabVIEW displays either the enable or clear input terminal, depending on the page you are configuring. To enable/reset all registers in the slice simultaneously, wire a TRUE value to this terminal.
• Select Terminals to Show—Enables the checkboxes below this pull-down menu. To display the terminal for an individual register, place a checkmark in the appropriate checkbox. The name in parentheses is the VHDL name of the enable or reset signal.
  Note If you select this option but LabVIEW still dims some checkboxes, you have not added the corresponding register on the Registers page. Click the Registers tab, place a checkmark in the appropriate checkbox, and then return to the Enable or Reset page.

After you click the OK button and return to the block diagram, LabVIEW displays any Boolean input terminals you selected. You then can write code to set these terminals to TRUE or FALSE at the appropriate times.

VHDL Equivalent of LabVIEW Options

To view the VHDL equivalent of a configuration, click the VHDL Instantiation tab. Refer to Table 1-3 in either the Virtex-5 FPGA XtremeDSP Design Considerations User Guide or the Virtex-6 FPGA DSP48E1 Slice User Guide, available on the Xilinx Web site at www.xilinx.com, for information about specific attributes. The following table shows the attributes that correspond to each option in LabVIEW.