Use the schematic at the bottom of the configuration dialog box to view the latencies of data paths within a DSP48E or DSP48E1 function. These latencies are the number of clock cycles data needs to flow from an input terminal to an output terminal. For example, a to p is one data path. b to p is another. Each register you add in a data path increases the latency of that data path by one clock cycle but does not affect the latency of other data paths. Therefore, the latencies of data paths can become unbalanced as you configure a function.

Whether this imbalance is acceptable depends on how you are using the function. Some applications do not require data paths with balanced latencies. For example, if you are wiring one function to another, imbalances within each function can be cancelled out by equal-but-opposite imbalances in other functions. However, some applications require data paths with balanced latencies. The following example shows a situation where balanced data paths are necessary.

Consider a function that is configured as a multiplier, p = a 2. That is, you wire the same value to both the a and b input terminals of the function. This value starts at 0 and increases by 1 every clock cycle. This DSP48E function contains the following data paths:

In this schematic, the a–>p data path contains the following three registers:

  • a register 2
  • m register
  • p

Because this data path contains three registers, the data path has a latency of three clock cycles. However, the b–>p data path contains only two registers and therefore has a latency of two clock cycles. This latency imbalance means that:

  • For the a–>p data path, the n th clock cycle uses the value of a from the (n – 3)th clock cycle
  • For the b–>p data path, the n th clock cycle uses the value of a from the (n – 2)th clock cycle

This imbalance makes it impossible to accomplish the goal of calculating p = a 2. The following table shows the inputs and output of this function during its first eight clock cycles:

Clock cycle Value of a Value of p Explanation
1 0 N/A Neither data path produces a value during this clock cycle.
2 1 N/A
3 2 0 The function multiplies the initialized value of the second register and 0 (value of a from the first clock cycle).
4 3 0 The function multiplies 0 (value of a from the first clock cycle) and 1 (value of a from the second clock cycle).
5 4 2 The function multiplies 1 (value of a from the second clock cycle) and 2 (value of a from the third clock cycle).
6 5 6 The function multiplies 2 (value of a from the third clock cycle) and 3 (value of a from the fourth clock cycle).
7 6 12 The function multiplies 3 (value of a from the fourth clock cycle) and 4 (value of a from the fifth clock cycle).
8 7 20 The function multiplies 4 (value of a from the fifth clock cycle) and 5 (value of a from the sixth clock cycle).

In this application, the imbalance of latencies causes incorrect calculations. In this situation, use the Registers page to add another register to the b–>p data path. If you do this, the schematic resembles the following illustration:

In the previous illustration, notice that both data paths have three registers, which means that for both data paths, the n th clock cycle uses the value of a from the (n – 3)th clock cycle.

The following table shows the inputs and output of this function during its first eight clock cycles:

Clock cycle Value of a Value of p Explanation
1 0 N/A Neither data path produces a value during this clock cycle.
2 1 N/A
3 2 N/A
4 3 0 The function multiplies 0 and 0 (value of a during the first clock cycle).
5 4 1 The function multiplies 1 and 1 (value of a during the second clock cycle).
6 5 4 The function multiplies 2 and 2 (value of a during the third clock cycle).
7 6 9 The function multiplies 3 and 3 (value of a during the fourth clock cycle).
8 7 16 The function multiplies 4 and 4 (value of a during the fifth clock cycle).

Now that the latencies of the data paths are balanced, this DSP48E function calculates p = a 2 correctly.