There are three rates involved in setting up a generation process.

  • Generation Sample Rate—The sample rate used by the digital-to-analog converter. This rate defines the ratio used in the fractional interpolator or frequency shift of the digital signal processing functions.
  • Maximum (Max) Generation Sample Rate—The rate at which data is transferred from the fractional interpolator in the DST firmware to the serial interface. If you have more than one channel activated, this rate is divided by the number of channels in your system.
  • I/Q Rate—The rate at which data is transferred from the memory of the waveform generator to the fractional interpolator in the DST firmware.
    • Note For protocols where each FPGA single cycle loop has a valid sample, the Generation Sample Rate and Max Generation Sample Rate are defined by the Data Clock Rate multiplied by the number of Samples per Cycle Per Channel.. Typically, the Generation Sample Rate and Max Generation Sample Rate values are the same; the DST host API reads the Max Generation Sample Rate from the firmware. For protocols where not every sample is valid, compile the DST bitfile with a Max Generation Sample Rate higher than the sample rate from the DUT specifications; then at runtime set the Generation Sample Rate with the DST API to match the sample rate from the DUT specifications.