There are three rates involved in setting up an acquisition process.

  • Acquisition Sample Rate—The rate at which the analog-to-digital converter samples the RF signal. This rate defines the ratio used in the fractional decimator or frequency shift of the digital signal processing functions.
  • Maximum (Max) Acquisition Sample Rate—The rate at which data is transferred from the serial interface to the fractional decimator in the DST firmware, which is defined by the frequency of the SCTL. If you have more than one channel activated, this rate is divided by the number of channels in your system.
  • I/Q Rate—The rate at which data is transferred from the fractional decimator in the DST firmware to the Multirecord Acquisition function. This defines the waveform rate acquired.
    • Note For protocols where each FPGA single cycle loop has a valid sample, the Acquisition Sample Rate and Max Acquisition Sample Rate are defined by the Data Clock Rate multiplied by the number of Samples per Cycle Per Channel. Typically, the Acquisition Sample Rate and Max Acquisition Sample Rate values are the same; the DST host API reads the Max Acquisition Sample Rate from the firmware. For protocols where not every sample is valid, compile the DST bitfile with a Max Acquisition Sample Rate higher than the sample rate from the DUT specifications; then at runtime set the Acquisition Sample Rate with the DST API to match the sample rate from the DUT specifications.