The Digital I/O Tests sequence simulates digital I/O channels or modules to demonstrate generation and measurement of digital state, digital pattern, clock, digital pulse, and PWM signals.

This TestStand sequence uses the LabVIEW measurement libraries. By default, the test sequence is installed to the following location: C:\Users\Public\Documents\National Instruments\PCB Assembly Test Toolkit for LabVIEW\TestStand\Automation\Digital IO Tests

Highlighted Features

  • Digital State Test—Uses digital output channels or modules to generate a digital high and low state and measure the digital states in test points with digital input modules. This example uses the following libraries:
    • DAQ_Static Digital State Generation
    • DAQ_Static Digital State Measurement
  • Digital Pattern Test (with trigger)—Uses digital output channels or modules to generate a digital pattern and measure the same signal with digital input modules. This example uses the following libraries:
    • DAQ_Dynamic Digital Pattern Generation
    • DAQ_Dynamic Digital Pattern Measurement
  • Digital Clock Tests—Uses digital I/O channels or modules to generate and measure the frequency of the a digital clock signal through counter-based measurements. This example uses the following libraries:
    • DAQ_Digital Clock Generation
    • DAQ_Digital Frequency Measurement
  • Digital PWM Test—Uses digital I/O channels or modules to generate a digital pulse signal and measure the Digital PWM parameters of the same signal through counter-based measurements. This example uses the following libraries:
    • DAQ_Digital Pulse Generation
    • DAQ_Digital PWM Measurement
  • Digital Count Event Tests - SW Timed (External Wait)—Uses digital I/O channels or modules to generate a digital pulse signal and count the number of digital edges present in the same signal through counter-based measurements. Digital edge counting is performed at software-timed intervals using an external wait. This example uses the following libraries:
    • DAQ_Digital Pulse Generation
    • DAQ_Digital Edge Count Measurement
  • Digital Count Event Tests - HW Timed (With Trigger)—Uses digital I/O channels or modules to generate a digital pattern and count the number of digital edges present in the same signal through counter-based measurements. Digital edge counting is performed at hardware-timed intervals using a trigger to create a measurement window for fixed duration. This example uses the following libraries:
    • DAQ_Digital Pattern Generation
    • DAQ_Digital Edge Count Measurement
  • Turn Off all DO Channels—Powers down all digital output channels by configuring the output state to LOW. This example uses the DAQ_Static Digital State Generation library.

    • Hardware Configuration

    The following figures illustrate the specific hardware connections for this example sequence using TestScale backplanes and modules. For NI 63xx (X Series) DAQ instruments, PFI signals are routed directly using the PFI resources available on the instrument connector. Refer to your hardware specifications to understand the available PFI routing signals for clocks and triggers.


    Refer to the documentation for your specific device for pinouts and other information necessary to adapt this example sequence to your application.

    Using the Sequence with Physical Hardware

    1. Run the sequence once in simulation mode. Running the sequence in simulation mode creates the required global virtual channels in NI MAX that you must modify.
      Note In this example, physical and global virtual channels are used to configure the terminal or pin to perform the instrument actions. Global virtual channels are software entities that encapsulate the physical channel along with other channel specific information such as range, terminal configuration, and custom scaling. You can create global channels in NI MAX and call them from measurement libraries.
    2. Right click the Import Hardware Config step and select Run Mode » Skip to skip the step.
    3. Configure the remaining sequences. Open each sequence and examine the Note to run with Hardware entry.
    4. Configure the Digital State Test sequence.
      1. Open NI-MAX and update the physical channel linked to the global virtual channels used in the Static Digital State Generation and Measurement initialize steps: TS_Din0, TS_Din1, TP_DOut0, TP_DOut1. Refer to Creating and Modifying Global Virtual Channels for more information.
      2. Review the digital input and digital output pin configurations for your application use case.
      3. Save the sequence.
    5. Configure the Digital Pattern Test (With Trigger) sequence.
      1. Open NI-MAX and update the physical channel linked to the global virtual channels used in the Static Digital State Generation and Measurement initialize steps: TS_Din0, TS_Din1, TP_DOut0, TP_DOut1. Refer to Creating and Modifying Global Virtual Channels for more information.
      2. Update the trigger as appropriate for your hardware configuration in Dynamic Digital Pattern Measurement - Configure TP step.
      3. Update parameters in the Generate Port Digital Data step based on the desired digital pattern. This step can also be replaced entirely with any other step to generate any custom digital pattern.
      4. Verify that the sampling rate at measurement end should be the same as the sampling rate at generation end. Use the onboard clock devices on the same backplane or use external PFI signals.
      5. Review the pin configurations for your application use case.
      6. Save the sequence.
    6. Configure the Digital Clock Test sequence.
      1. Update the terminal and counter channels used in the initialize step.
        • Physical Counter: Simulated_DAQ/ctr1, Simulated_DAQ/ctr3
        • Terminals: /Simulated_DAQ/PFI3, /Simulated_DAQ/PFI7
      2. Update the digital clock settings in the Digital Clock Generation - Configure and generate Digital clock step based on the generated digital clock signal.
      3. Review the pin configurations for your application use case.
      4. Save the sequence.
    7. Configure the Digital PWM Test sequence.
      1. Update the terminal and counter channels used in the initialize step.
        • Physical Counter: Simulated_DAQ/ctr1, Simulated_DAQ/ctr3
        • Terminals: /Simulated_DAQ/PFI3, /Simulated_DAQ/PFI7
      2. Update the cycles to capture in the Digital PWM Measurement - Configure only step.
      3. Update the digital pulse settings in the Digital Pulse Generation - Generate Digital pulse signals step based on the generated digital pulse signal.
      4. Review the pin configurations for your application use case.
      5. Save the sequence.
    8. Configure the Digital Count Event Tests - SW Timed (External Wait) sequence.
      1. Update the terminal and counter channels used in the initialize step.
        • Physical Counter: Simulated_DAQ/ctr1, Simulated_DAQ/ctr3
        • Terminals: /Simulated_DAQ/PFI3, /Simulated_DAQ/PFI7
      2. Update the digital pulse settings in the Digital Pulse Generation - Configure & Generate Digital pulse signals step.
      3. Update the external software wait time in the External Software Wait step based on the measurement window required to capture the entire digital pulse signal.
      4. Review the pin configurations for your application use case.
      5. Save the sequence.
    9. Configure the Digital Count Event Tests - HW Timed (With Trigger) sequence.
      1. Update the terminal and counter channels used in the initialize step.
        • Physical Counter: Simulated_DAQ/ctr0, Simulated_DAQ/ctr1
        • Terminals: /Simulated_DAQ/PFI0
        • Global Channel: TS_Din0
      2. Update the trigger as appropriate for your hardware configuration in Digital Edge Count Measurement - Configure TP step.
      3. Update parameters in the Generate Port Digital Data step based on the desired digital pattern. This step can also be replaced entirely with any other step to generate any custom digital pattern.
      4. Review the pin configurations for your application use case.
      5. Save the sequence.
    10. Configure the Turn Off all DO Channels sequence.
      1. Open the Initialize step and update the Global Channels input to use yourdigital output channel.
      2. Review the digital output pin configurations for your use case.
      3. Save the sequence.

    Physical Hardware Considerations

    Ensure a common ground connection is provided between digital input and digital output resources.

    In digital pattern measurement, make sure to use the same sample clock rate in both digital input and digital output for precise data extraction from the testpoint.

    Digital states are provided as True or False Boolean values to the VIs. The corresponding voltage level, for example, a digital HIGH state, depends on individual resources.

    (TestScale only) TS-15050 DIO channels use 3.3 V TTL, single-ended I/O. The TS-15120 DIO voltage level is controlled by manual jumper connections. TS-15130 DO channels are current sinking outputs. Refer to the individual product documentation for additional details.