The possible application-specific FPGA enhancements are limited only by the nature of the instrument I/O, but for test applications they can be divided into five broad categories. These include on-FPGA measurements and stimulus generation, closed-loop or protocol-aware test, custom triggering and data reduction, deterministic test execution and DUT control, and DUT or application-specific personalities. Each of these enhancements are ultimately designed to lower the total cost of test by delivering higher test throughput, providing hardware re-use and future-proofing, or by enabling new and innovative tests not previously possible.
On-FPGA measurements and stimulus generation move these tasks from the host processor to the FPGA, either completely or even partially. When implemented on the processor, measurements and stimulus generation are not typically real-time, as the time to compute measurements or generate waveforms is longer than the waveforms themselves. On the FPGA these algorithms can be computed in real-time, however, so they can be executed continuously and virtually instantaneously. This might deliver higher test throughput by reducing the measurement computation time, or it might enable new types of tests by performing measurements continuously over an indefinite period or by generating long-duration non-repetitive waveforms. Examples of these types of FPGA enhancements include RF spectral measurements, digital bit error rate calculation, phase-continuous tone generation, or intentional waveform impairments such as distortion or noise.
Figure 5. On-FPGA Measurements and Stimulus Generation
Closed-loop or protocol-aware test takes advantage of the FPGA’s determinism and low-latency decision-making to interact with the DUT in real time. This might reduce the burden on the host processor to deliver higher test throughput, it might facilitate the evolution of communication protocols to enable hardware re-use, or it might enable new types of real-time, closed-loop tests which were not previously possible. Examples of these FPGA enhancements include emulating the DUT’s real-world operating conditions such as through channel emulation or by emulating the device to which the DUT will eventually interact, or by implementing digital or RF communications protocols on the FPGA.
Figure 6. Closed-Loop or Protocol-Aware Test
Custom triggering and data reduction aims to isolate the minimum amount of data required to make a particular measurement, reducing the amount of subsequent processing on either the FPGA or host microprocessor. This might deliver higher test throughput by reducing the measurement computation time, it might enable hardware future-proofing by allowing the addition of new instrument capabilities over time to gain additional insight into ever-evolving signals of interest, or it might enable new and innovative measurements by capturing rare events with 100% confidence. Examples of these FPGA enhancements include frequency domain triggers, real-time time domain envelope triggers, pulse triggers, and time or frequency domain decimation.
Figure 7. Custom Triggering and Data Reduction
Deterministic test execution and DUT control moves the sequencing and decision-making from a software test executive into hardware logic, where it runs as fast as possible with complete determinism. DUT control typically involves communicating with the device under test through some type of digital protocol in order to change its operating mode over the course of the test sequence, if necessary. An FPGA-based state machine can then replace the software test executive and control the software-designed instrument signal generation and/or acquisition, the digital DUT control, and even other instruments in a PXI system through the backplane trigger lines. This type of FPGA enhancement is purely designed to deliver higher test throughput in very high volume automated test applications where the savings of even milliseconds is very valuable. Examples of digital DUT control protocols include I2C, SPI, JTAG, and RFFE, and hardware test sequencer and DUT instruction sequencer IP facilitate hardware-based test execution.
Figure 8. Deterministic Test Execution and DUT Control
DUT or Application-Specific Personalities combine the various FPGA enhancements described above to deliver FPGA features optimized for specific devices under test. Theses personalities can be reconfigured over the course of testing a single device, or they may be swapped when an instrument is re-purposed for testing a different device. The former scenario might occur when a single software-designed instrument is performing the function of several traditional instruments. The latter scenario might occur frequently in a high-mix testing environment where many devices share a common assembly line, or less often in high-volume environments when hardware is reused after the prior device is at the end of its life and is no longer in production. Regardless, the benefit is hardware re-use, cutting down on capital cost. An example of this kind of FPGA enhancement is updating the digital protocol in a protocol-aware test as new features or increased performance are added to the protocol specification.
Figure 9. DUT or Application-Specific Personalities