Benefits of SMC-Based Arbitrary Waveform Generators for I/Q Signal Generation

Overview

Digital communications systems are now pervasive in society. Their reduced power consumption, spectral efficiency, higher quality, and cost advantages are so strong that the entire analog television infrastructure is being overhauled to use digital communication methods. In the faster-moving cellular communication market, digital systems replaced analog systems about a decade ago and have evolved from frequency-division-multiple-access and time-division-multiple-access systems to GSM and CDMA systems. Because numerous digital communications system architectures represent data symbols in the rectangular form with in-phase (I) and quadrature (Q) signals, engineers must be able to generate precise baseband I/Q signals for research and design and manufacturing test.

In research, a flexible I/Q generation system is key to rapidly prototyping and evaluating new modulation schemes and transmitter/receiver architecture performance. During new product design, I/Q signals test a variety of I/Q modulator/demodulator physical layer parameters, such as phase and amplitude balance, DC offset, and input compression point. These parameters are also tested in manufacturing to ensure minimal gain and phase error – two parameters critical in reducing error vector magnitude and correctly transmitting data.

Arbitrary waveform generators such as the NI 5421, which are based on the NI Synchronization and Memory Core (SMC) architecture, offer several benefits for generating baseband I/Q signals for both the design and testing of digital communications systems. Specifically, the NI 5421 generators feature:
  • Multimodule synchronization for independent control of the phase, amplitude, and offset of I-, I+, Q-, and Q+ signals
  • 2x, 4x, or 8x data interpolation for effective sampling rates up to 400 MS/s
  • Increased test throughput by rapidly downloading test waveforms using the PCI bus
  • Large onboard waveform memory for long play times

Contents

Synchronization for Maximum Flexibility

In addition to requiring minimal distortion and low jitter, I/Q general applications require accurate control of the signal amplitude, phase, and DC offset. Amplitude, phase, and offset are usually the three parameters that are varied during modulator tests. The modulator/demodulator input circuitry is typically differential, consisting of I-, I+ and Q-, Q+ signals. Although you can generate a differential signal with a single AWG by using a transformer, you must generate four independent signals to fully stress a circuit design and explicitly control the phase, amplitude, and offset parameters within the differential I-, I+ and Q-, Q+ pairs, and the I/Q pair. Traditional I/Q generators cannot adjust the parameters within a differential pair. You can achieve this flexibility only by synchronizing independent arbitrary waveform generators. However, when synchronizing different AWGs to create differential signals, attention must be paid to the channel-to-channel skew and jitter, which will distort the differential signal.

Proper synchronization requires precise sample clock skew control, trigger propagation and skew control, and a low-jitter reference clock. This kind of synchronization is often difficult or impossible using traditional GPIB-based AWGs. You must use external cables and reference clocks, and even then results are questionable. The built-in triggering lines and 10 MHz reference oscillator of the PXI platform make synchronizing instruments with reliable results much easier. Additionally, NI's patent-pending T-Clock synchronization provides a mechanism to adjust the sample clock skew in approximately 20 ps increments to remove trigger skew effects.

T-Clock Multimodule Synchronization
Because NI 5421devices are built on the SMC architecture, it is capable of precise T-Clock synchronization (See National Instruments Synchronization and Memory Core: A Modern Architecture for Mixed Signal Test). T-Clock sends and receives triggers relative to a clock signal much slower than the AWG sample clock. To generate this clock signal, called T-Clk, the sample clock on each device is divided down to a rate ≤10 MHz. The T-Clk on each device is automatically aligned using a time-to-digital converter (TDC) to measure T-Clk skew relative to the 10 MHz PXI reference clock. To send a start trigger, the master AWG pulses a trigger line synchronous to the T-Clk falling edge. All receiving AWGs (including the master AWG itself) receive the trigger pulse and start generating on the next rising edge of the T-Clk. Because the T-Clk period is 100 ns or greater, there is plenty of time for the trigger pulse to propagate to all devices before the next rising edge occurs, to ensure that all the generators start at the same time.

This method results in a channel-channel skew of ≤500 ps. To achieve even less skew, you can connect the AWG outputs to a multichannel, high-bandwidth oscilloscope to make a more precise phase measurement than the onboard TDC. The easiest method to measure the phase is to configure the AWGs to generate sine or square waves and examine the phase difference at the zero voltage crossing. You then input your measurement into the NI T-Clock software, overriding the TDC-measured results. With external oscilloscope measurements, the skew can be reduced to 10 to 20 ps. Figure 1 shows two synchronized PXI-5421 module outputs, producing 10 MHz sine waves after manually adjusting the sample clock delay. This figure shows the skew to be approximately 10 to 20 ps. At 10 MHz, 10 ps of skew translates to 0.036 deg of phase, much less than the 0.1 deg required by most I/Q applications. By using the sample clock delay adjustment value, the skew can vary a maximum of ±1 sample clock period in < 20 ps increments. If a larger phase adjustment is required, you can move samples at the beginning of one of the waveforms to the end for positive phase, or from the end to the beginning of the waveform for negative phase. This method provides coarse control, while the sample clock delay adjustment provides fine control.


Figure 1. Two PXI-5421 modules produce 10 MHz tones with <20 ps of channel-channel skew.


The <20 ps resolution in sample clock delay adjustment can be considerably improved by using the PXI-5421 high-resolution clock mode generated by an Analog Devices 9852 direct digital synthesis (DDS) chip. The AD9852 features a 14-bit programmable phase-offset register, which means you can adjust the sample clock phase by [(sample clock period)/16384] seconds. For instance, if the sample clock frequency is 100 MS/s, you can adjust the phase in 610 fs (femtoseconds) increments. However, given that the PXI-5421 system jitter is approximately 4 ps when using the high-resolution clock, you can observe this precise phase control only by examining a phase measurement histogram over many output waveform cycles. The caveat to using the high-resolution clock is the higher clock jitter inherent with DDS clock generation. The jitter produces increased I/Q signal phase noise. For the best possible phase noise performance, use the divide-down clock mode, which has a phase noise of -137 dBc/Hz at 10 kHz offset from the carrier.

In addition to providing precise phase offset control, the high-resolution clock delivers 1.06 µHz sample clock frequency tuning resolution, essential for obtaining the proper digital communications systems chip rates. For instance, the chip/symbol rates for WCDMA and CDMA2000 are 3.84 and 1.2288 MHz respectively. Typically, these signals are represented with four samples per symbol, resulting in 15.36 and 4.9152 MHz sampling rates. The high-frequency resolution of the PXI-5421 helps by generating the proper sample rate for the waveform and, in receiver stress testing, by precisely altering the playback frequency to test receiver frequency sensitivity.

Because two separate AWGs create the differential signal, channel-to-channel jitter is the main contributor to distortion so it is critical that jitter be as low as possible. To measure the jitter, we connected two AWGs generating 10 MHz square waves to a Tektronix CSA8000 communications signal analyzer. One of the square wave signals externally triggers the signal analyzer, while the second signal connects to CH 0. A histogram of the jitter at the zero crossing was made and is shown in Figure 2. The rms jitter is 2.954 ps, with 95.7 percent of the data within 2σ of the mean value. Additionally, the histogram has a Gaussian distribution, indicating that the jitter arises from the random noise processes present in all electronics.


Figure 2. The PXI-5421 channel-channel jitter is 2.954 ps.


Despite the high-performance synchronization of T-Clock, the NI T-Clock application programming interface (API) offers straightforward functions used to synchronize the four AWGs. The first VI sets all devices to phase lock to the PXI 10 MHz reference clock and configures the start triggers. The next VI performs the T-Clock alignment, synchronizing all AWG T-Clks. It then begins generation, and the program pauses until generation completes. A simple example is shown in Figure 3.



Figure 3. Four VIs perform the necessary tasks for precisely synchronizing the AWGs.

See Also:
National Instruments Synchronization and Memory Core: A Moderm Architecture for Mixed-Signal Test

Differential Signaling Using RF Transformers


Some production test systems do not require independent signal phase, amplitude, and DC offset control within the differential I and Q pairs. For these applications, two single-channel AWGs with some external signal conditioning circuitry accomplish the task. In this configuration, you still have phase, amplitude, and DC offset control between the I and Q signals, just not within the I-, I+ and Q-, Q+ differential pairs.

The required external conditioning circuit is fairly straightforward. Using an RF transformer, the single-ended AWG output is converted to a balanced differential signal. By using a center-tapped transformer, you can also apply a DC offset to the balanced signal by using a low-cost analog output module.

Insertion loss, a key specification when selecting an RF transformer, is the ratio of power lost from the transformer input to output. The insertion loss varies over input frequency and thus distorts signals of appreciable bandwidth. Make sure to choose a transformer that has low insertion loss over your signal bandwidth.

Additionally, select a transformer with a center-tapped secondary winding. By connecting the center tap to the analog output module, such as the NI PXI-6704 16-bit analog output module, you can apply a DC offset to the balanced signal. Because most I/Q applications require a DC offset of ±1.5 V, use a resistive circuit divider on the PXI-6704 output to reduce its ±10 V output, thereby maintaining the full 16-bit amplitude control over the smaller voltage range.

Because the upper and lower side center tap windings are rarely identical, add a bypass capacitor to the circuit to maintain the center tap at an AC ground level to maintain transformer balance. The complete circuit is shown in Figure 4.




Figure 4. You can use a center-tapped RF transformer with a voltage divider and capacitor to generate differential signals with a single AWG.

Insertion loss and impedance mismatches make the signal amplitude at the transformer output smaller than the intended amplitude present at the AWG output. If the insertion loss is constant over the desired frequency range, it can be approximately modeled by a resistance. Simply add this resistance to the transformer input impedance to calculate the effective impedance seen through the transformer. An NI-FGEN driver function call uses this value to adjust the NI 5421 output voltage to compensate for the impedance mismatch between the transformer and the NI 5421 50 Ω output.

Data Interpolation for Improved Spectral Purity


I/Q signal generation applications place high demands on signal generator spectral purity. To minimize distortion from the digital-to-analog reconstruction images, NI 5421 generators use a combination of digital and analog filtering designed to optimize passband flatness, phase linearity, and image suppression.

You must update the DAC samples at least twice as fast as the bandwidth of the analog signal you wish to accurately generate. Even though the theoretical requirement for sample clock (fs) is twice that of the signal bandwidth (fo), images are introduced in the output signal at |fo ± nfs|, as shown in Figure 5. These images, which degrade the signal spectral purity, must be removed with a lowpass filter.

 



Figure 5. Digital-to-analog signal reconstruction creates undesired sampling images.

To understand data interpolation and its effects on spectral purity, suppose there are three different analog filters with varying cutoff frequencies and orders. The three filters are represented in Figure 6 along with the sampling images. The ideal analog filter is represented as "analog filter 1." Because this filter attenuation is very steep, it is also very expensive to implement, and requires a large amount of board space. Additionally, it cannot achieve the passband flatness required for I/Q applications. Analog filter 2 represents a more practical filter; however, it will not attenuate the images near fs. Because analog filters have trade-offs between the attenuation steepness after the cutoff frequency and the flatness before the cutoff frequency, selecting the ideal filter values heavily depends on the DAC sampling rate and the waveform frequencies generated. It is impossible to design a single analog filter that accommodates flexible sample rates and output signal frequencies while maintaining strict performance requirements.

Another critical analog filter specification is group delay - the amount of time needed for a signal having finite time duration (such as a pulse) to pass through the analog filter. In an ideal filter with linear group delay, all frequencies present in the signal have the same time delay, so that the output signal is not phase-distorted.

The third filter, analog filter 3, has a much higher cutoff frequency than the first two analog filters. Because of the higher cutoff frequency, the filter is very nearly flat in the passband (0 to 0.43fs). The images produced at fs and 2fs fall within the passband of filter 3, so they are not attenuated at all, but this shortcoming can be alleviated with a digital interpolation filter.

 

 


Figure 6. Sampling images must be filtered to improve spectral quality, but different filter implementations must be considered.

To simplify the analog filter requirements and achieve good specifications for a range of sampling rates and output frequencies, the NI 5421 devices use a half-band finite impulse response digital filter to interpolate one, three, or seven samples between every two waveform samples at two times, four times, and eight times the sampling frequency (fs). The DAC then internally operates at an effective sampling rate that is two times (2fs), four times (4fs), or eight times (8fs) the sampling frequency - specifically, the rate at which the data is clocked from the memory into the DAC.

In Figure 7, using a two times-interpolating filter increases the DAC effective sampling rate to 2fs. The first set of reconstruction images is now located at |2fs ± fo|, which falls in the filter 2 stop band.



Figure 7. Interpolation increases the sampling rate, causing the images to shift to higher frequencies.

Now, analog filter 2 can easily filter out all the images caused by the digital signal generation, as seen in the frequency-domain representation in Figure 7, and in the time-domain representation in Figure 8.

 


Figure 8. In the time domain, interpolation has the effect of smoothing otherwise sharp sample transitions.

Using 2x interpolation filtering and increasing the DAC effective sampling rate to 2fs better eliminates images, and generates a signal with better spectral purity. However, increasing the interpolation filter to 4x further improves the output signal.

Figure 9 shows a signal image with 4x interpolation and a DAC effective sampling rate of 4fs. The images are shifted up to 4fs, where they are well above the filter 3 cutoff frequency. This configuration, used in the NI 5421, eliminates the spectral images and has a maximally flat filter within the passband. The configuration approaches an ideal design in digitally generating spectrally pure waveforms. An NI 5421 achieves ±0.25 dB passband flatness to 40 MHz and a total harmonic distortion of -75 dB at 1 MHz.

 

 


Figure 9. The combination of digital interpolation and analog filter results in the best flatness and image rejection.

Reduced Waveform Download Time with PCI/PXI


Digital communications systems test waveforms can become quite large. For instance, in generating a WCDMA signal with a pseudorandom noise (PN) sequence order equal to 16 (65,635 symbols), the resulting signal occupies 3.15 MB. To increase the measurement statistical confidence, larger PN sequences should be used. Downloading waveforms that are more than a few hundred kB with GPIB (IEEE 488 bus) can become prohibitively slow and will significantly impact test throughput. Although high-speed GPIB (HS488) is an IEEE standard, very few instruments implement the 8 MB/s data transfer mode. Typically, GPIB-based instruments achieve throughput rates of 200 to 300 kB/s, even though the GPIB standard specifies a theoretical rate of 1 MB/s.

Using a highly optimized driver and the SMC architecture, an NI 5421 can attain download rates up to 84 MB/s for large downloads. This rate can be attributed to the high-throughput PCI bus; however, as with GPIB, few plug-in boards actually attain data transfer rates even close to the 132 MB/s theoretical maximum throughput of PCI.

 

Waveform Size
(I16 samples)
NI 5421 Average Time (s)
GPIB AWG Average Time (s)
PCI/PXI Speed Advantage
10,000
0.000610
0.151
247x
50,000
0.001924
0.807
419x
100,000
0.003442
1.724
501x
500,000
0.012714
8.149
641x
1,000,000
0.025005
16.460
658x


Table 1. The high-throughput PXI platform is 247x to >650x faster than GPIB for downloading data to an AWG.

Deep Memory for Long Play Times


The SMC architecture offers up to 256 MB of memory for a single-channel NI 5421 arbitrary waveform generator. Because each sample is 16 bits, the memory size (in samples) is 128 MS. Clocked at 100 MS/s, this results in a 1.28 s play time. Using the NI 5421 digital interpolation, the play time can be extended to 2.56 s in the 8x interpolation mode. Data clocked into the DAC at 50 MS/s will be interpolated to 400 MS/s before conversion to an analog signal. In generating trellis plots and constellations, and computing bit error rate, a large data set will always help the statistical confidence of the measurement. Deep memory greatly improves measurement realism by generating as long an aperiodic signal as possible. By using an AWG with a small amount of memory and looping to create a large signal, the device will not be thoroughly tested, because the periodic signal elements will feed through to the measurement results. Because pseudorandom sequences are a critical tool in characterizing communications systems performance, long aperiodic signals generated by deep-memory AWGs are essential for making statistically significant measurements.

Creating I and Q Data


You can use a number of tools to create I and Q waveform sample data. Commonly, data resulting from simulations using a math package such as MATRIXx X-Math, or The MathWorks MATLAB® software are stored to disk. National Instruments LabVIEW and LabWindows/CVI can read a variety of data and convert it to either I16s or double-precision, floating-point numbers - two formats that the NI-FGEN driver directly accepts. By first normalizing the waveform data to ±1 V and extracting the gain multiplier, the AWG can use the full 16-bits of the DAC and amplify or attenuate the output signal using the front-end analog electronics to ensure the best output signal quality.

LabVIEW can also directly generate I/Q data using the NI Modulation Toolkit. The Modulation Toolkit provides LabVIEW VIs for modulating and demodulating both analog and digital schemes such as AM, FM, PM, QPSK, and QAM. Figure 10 shows how to use the toolkit to create I and Q data for a frequency-modulated (FM) signal. With the first VI, you generate the FM message signal by selecting from standard waveforms such as sine, square, or triangle, and specifying the carrier frequency and frequency deviation. The next VI performs the modulation and returns the complex envelope of the FM signal. Lastly, two VIs extract I and Q data from the complex envelope signal and download it to the AWGs. The toolkit can also modulate a user-defined message signal and extract the modulated signal magnitude and phase (polar form) components to test a polar-based digital modulator. The programming for creating waveforms with different modulation schemes (such as QAM and QPSK) follows a similar structure.



Figure 10. Creating the I and Q Waveform Data for an FM Signal Using the NI Modulation Toolkit for LabVIEW

To rigorously test a demodulator design using the Modulation Toolkit, you can add impairments such as quadrature skew and additive white Gaussian noise (AWGN) to the I and Q signals to more accurately reflect real-world operating conditions. To model channel effects, the Modulation Toolkit offers Rayleigh and Rician fading profiles, or you can create your own custom-defined fading profile based on the simulation tool output.

Conclusion


The NI SMC-based arbitrary waveform generators have several advantages over traditional instruments. The tight synchronization of the SMC T-Clock technology makes it possible to create an I/Q signal generator with fully independent gain, amplitude, and phase control. Additionally, the SMC-optimized PCI/PXI interface and driver software deliver outstanding download rates that reduce precious test time and increase test throughput. The deep memory reduces the test signal periodicity, resulting in better device performance assessment. These benefits, along with intuitive driver software and world-class analog specifications, make the SMC-based NI 5421 devices an excellent choice for generating I/Q test signals.