When referencing multiple modules in one task, the same sampling rate will apply to all channels. However, some applications may require synchronization at different rates.
Two SAR Modules - You do not need to do any additional work to synchronize two SAR Modules or Slow Sampled modules acquiring at different rates in a CompactDAQ chassis or controllers besides sharing a Start Trigger. The sample clock each module uses is derived from the same signal. Thus, the measurements will be synchronized if the modules are in the same chassis.
Two DSA Modules - To synchronize two Delta Sigma Modules acquiring at different rates, set the tasks to share a common master timebase, synchronization pulse (sync pulse), and start trigger. The master timebase clock is routed from one module to another in the Figure 6. Note that the NI DAQmx Timing Property node SampleClck.Timebase.Src refers to the same 12.8 MHz or 13.1 MHz signal as the master timebase listed in the Operating Instructions and Specifications/Datasheet. This clock is also known as an oversample clock because there are many ticks of this clock required to produce one sample.
Figure 6: Sharing the over sample clock
A device that uses a Delta Sigma Module has a free-running ADC. Sharing the master timebase will ensure that measurements are derived from the same clock, but there will be an unknown phase shift due to the exact start of the ADC. The next step is sharing the synchronization pulse. The sync pulse is used to reset the ADC/DAC before it begins acquiring or generating samples. Without this signal to reset the ADC/DAC, measurements taken will not be synchronized. Below, the property nodes are shown that allow the sharing of an oversample clock and a sync pulse.
Figure 7: Sharing over sample clock, start trigger and sync pulse.
The above configuration routes the synchronization pulse from one task to another depending on which task is running at a faster rate. For multirate configuration, we use the sample clock of the slower running task to trigger the faster running task. The reasoning for this is explained in the example.
One more consideration to study is the reset time required by each module. The reset time is a delay required by a Delta Sigma Modules ADC after it has received the synchronization pulse until it begins acquiring data. Different model Delta Sigma Modules may have different reset times. You need to account for this reset time to ensure each device has gone through the reset sequence and begins to acquire or output samples at the same time. To properly account for potentially different reset times, the reset time required for each module is checked and, if necessary, a delay added to modules with a shorter reset time. Therefore, the sum of the reset time and the delay should be the same for each module.
The time needed to reset the ADC can be found using the DAQmx Timing Property Node SyncPulse.ResetTime. To ensure all ADCs end their reset cycle coincidentally, a comparison is made between both tasks’ reset time. We take the task with the largest Reset Time and subtract the Reset Time of the task with the smaller Reset Time. The result is the time where the one task has begun to acquire data while the other task is still going through its reset cycle. To account for this delay we use another NI-DAQmx property called SyncPulse.ResetDelay. This property allows a delay in the sync pulse that will be sent to each module. As previously stated the reset time is the delay between when the ADC receives a sync pulse and begins to acquire data. To best use this property, you should set this equal to the difference between the module that has the greatest reset time and the reset time of the module. This will shift the synchronization pulse of a module that takes less time to reset thus ensuring that both modules with a slow and fast reset time end their reset sequence at the same time. The code below details how to get the reset time and determine the appropriate reset delay.
Figure 8: Sync Pulse reset time query and calculating the reset delay
The NI-DAQmx property node SyncPulse.ResetDelay has a maximum input of .013 seconds, which may not be suitable for large differences in the Reset Delay values of differing modules. Note the order of the property node when polling for the SyncPulse.ResetTime on the task receiving the master timebase. The value will change depending on a 13.1 MHz Timebase or 12.8 MHz Timebase. Thus, it is important to call the SyncPulse.ResetTime on this task after the module has been informed of the Master Timebase’s rate.
When searching for the properties SyncPulse.ResetDelay and SyncPulse.ResetTime, you will also encounter SyncPulse.SyncTime and SyncPulse.MinDelaytoStart. Most developers will not use this property but may encounter them due to their similarity in name and proximity in location. SyncPulse.SyncTime is the SynchPulseResetTime y plus the value you enter for SyncPulse.ResetDelay. The value of SyncPulse.SyncTime is rounded to the nearest millisecond. SyncPulse.MinDelaytoStart is the time between when the Synchronization Pulse is issued and master task issues the start trigger. This property is equal to SyncPulse.SynchTime unless explicitly set.
Two Reference Clocked Modules -To synchronize two Reference Clocked Modules at different rates (like two DSA Modules), distribute the master task’s reference clock, synchronization pulse, and sample clock to other tasks. Note that the NI DAQmx Timing Property node RefClck.Src refers to the same Internal master timebase listed in the Datasheet.
Figure 9: Synchronizing Two Reference Clocked Modules
Delta Sigma Module and SAR/Slow Sampled Module – To synchronize a Delta Sigma Module and SAR/Slow Sampled Module, share the Delta Sigma Module’s master timebase and sample clock with the SAR/Slow Sampled Module. Since the SAR/Slow Sampled Module cannot acquire at 12.8 MHz or 13.1 MHz the Delta Sigma’s master timebase is shared with the master timebase of the SAR/Slow Sampled Module as depicted in figure 10. The sample clock of a SAR/Slow Sampled Module is typically derived from the CompactDAQ Chassis or Controller’s onboard clock. This method replaces the chassis or controller clock with the 12.8 MHz or 13.1 MHz clock from the Delta Sigma Module.
Figure 10: Synchronizing a Delta Sigma Module and SAR/Slow Sampled Module
Reference Clocked Module and SAR/Slow Sampled Module – To synchronize a Reference Clocked Module and SAR/Slow Sampled Module, share the Reference Clocked Module’s reference clock and sample clock with the SAR/Slow Sampled Module. Since the SAR/Slow Sampled Module cannot acquire at 12.8 MHz, the Reference Clocked Module’s reference clock is shared with the master timebase of the SAR/Slow Sampled Module. The sample clock of a SAR/Slow Sampled Module is typically derived from the CompactDAQ Chassis or Controller’s onboard clock. This method replaces the chassis or controller clock routed to the SAR/Slow Sampled Module with the Internal Master Timebase from the Reference Clocked Module.
Figure 11: Synchronizing a Reference Clocked Module with a SAR/Slow Sampled Module