Wafer-Level Parametric Test
Wafer-level test engineers need to reduce test time without sacrificing measurement quality and accuracy.
As IC manufacturers continue to introduce new and innovative processes with decreasing device geometries, they need to ensure the additional complexity from these changes does not affect the long-term reliability of their ICs. As technologies evolve at a rapid pace, semiconductor manufacturers must increase the amount of reliability data they collect and analyze while decreasing the cost of test. When faced with this problem of more data at a lower cost, many reliability engineers find they cannot solve it using traditional reliability solutions, so they are turning toward modular, flexible solutions that can scale to fit their needs.
Learn more about how you can lower your test cost with a platform-based approach to semiconductor test.
Use the PXI platform to reduce test time, decrease cost by 75 percent, and perform process experiments that were previously impossible.
PXI provides the foundation for high-uptime, SMU-per-pin wafer-level reliability systems powered by the latest commercial processors and best-in-class PXI SMU portfolio.
NI SMUs combine the power and measurement performance of traditional box SMUs with NI technology that makes them smaller, faster, and more flexible.
The NI Partner Network is a global community of domain, application, and overall test development experts working closely with NI to meet the needs of the engineering community. NI Partners are trusted solution providers, systems integrators, consultants, product developers, and services and sales channel experts skilled across a wide range of industries and application areas.
PXI Platform Resource Kit
Learn the basics of the PXI platform for semiconductor characterization with architectural notes, relevant case studies, and performance metrics.
An NI Partner is a business entity independent from NI and has no agency, partnership, or joint-venture relationship with NI.