The LabVIEW FPGA Module includes several execution modes. Each execution mode offers different functionality for testing and debugging an FPGA VI. You can change the execution mode by right-clicking the FPGA target in the LabVIEW project and selecting Select Execution Mode from the shortcut menu.
Figure 1. Selecting Execution Mode within the LabVIEW FPGA project.
Executing on the FPGA hardware is typically reserved for the final stages of testing a LabVIEW FPGA design. This execution mode is the most representative of how a system will behave in deployment, however debugging options are limited mode.
Simulation (Simulated I/O)
Most LabVIEW FPGA users will execute the majority of testing in this mode. Simulation mode utilizes an advanced simulation engine to execute a VI on the desktop, but with timing characteristics similar to the FPGA hardware. Simulation mode with simulated I/O offers several advanced mechanisms for validating code with simulated values for I/O. The simulated values can be arbitrary or defined.
Simulation (Real I/O)
In this mode, real data is acquired from the inputs of the FPGA target, passed to the host computer, and consumed in the simulation environment. Changing FPGA output values in simulation results in the physical changes to the FPGA hardware output. This execution mode is reserved for R Series targets only.
This execution mode relies on advanced third-party software and VHDL test benches to provide a full cycle-accurate simulation of FPGA code. Third-party simulation mode also allows for verification of HDL IP integrated through the CLIP or IP Integration Node.