LabVIEW FPGA Code Simulation


Simulation is an important step in the FPGA design flow. Simulation has increasingly become important to validate IP before committing to a time-intensive compilation process and debugging the design with high-fidelity test coverage.


  Using the LabVIEW FPGA Desktop Execution Node
The LabVIEW FPGA Desktop Execution Node, available in FPGA simulation mode, enables you to create test benches with accurate timing characteristics. This tutorial introduces the concepts necessary to effectively use the FPGA Desktop Execution Node.
  Cycle-Accurate Simulation in LabVIEW FPGA
Simulate your application logic for both functionality and timing. Cycle-accurate simulators test the timing constraints of your application by providing a means to validate the signal propagation of your logic.
  Cycle-Accurate Simulation with Xilinx Isim
A cost-effective method to perform timing simulation on your LabVIEW FPGA application, if you are familiar with VHDL, is to use the included Xilinx ISim cycle-accurate simulator.
  Cycle-Accurate Co-Simulation with Mentor Graphics ModelSim
Take advantage of these standard simulation packages, the NI LabVIEW FPGA Module interfaces with two third-party simulators: Mentor Graphics ModelSim and Xilinx ISim.

Main Page: Everything You Need to Know About LabVIEW FPGA
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