The DRAM interface signals are synchronous to the DRAM interface clock. Synchronization registers cause a delay in sending and receiving data or commands to and from the DRAM interface. For proper device operation, you must disable all synchronization registers for all DRAM interface signals and all input signals. Always disable synchronization registers for synchronous interfaces when proper operation depends on no latency.

Note All NI PXI version 1.1 and later CLIP items and all NI PXI Express CLIP items automatically disable all synchronization registers
  1. Right-click a DRAM interface signal and select Properties from the shortcut menu to open the FPGA I/O Properties dialog box.
  2. Select Advanced Code Generation in the Category list to open the Advanced Code Generation page.
  3. Select 0 in the Number of Synchronizing Registers for Output Data box to disable all synchronization registers for that signal.