NI Data Link System Component FPGA API

The DLsc FPGA API is designed to be used in the LabVIEW FPGA environment.

The DLsc FPGA API enables creation of endpoints. Endpoints provide read and write access to target-specific CLIPs. The CLIPs define streaming protocols using the device MGTs (multi-gigabit transceivers). You can connect to devices with compatible endpoints using the defined ports on the instrument front panel. Refer to Connecting the Hardware for supported connections.

The following diagram displays the following:

  • The connections of the endpoint
  • The connections of the endpoint collection functions
  • Outlines the decisions made during FPGA code generation
  • How the data flow changes based on the user inputs
Figure 4. NI Data Link System Component FPGA API Flow Chart
Table 1. FPGA API Supported User Configurations
Link Direction Polymorphic Selector (TX, RX, DX)
Link Type Constructor Type (Aurora 64B/66B)
Data Type Polymorphic Selector (32 bits (16i,16q) at 1, 2, 4, 8, 16, 32 SPC)
Buffer Process Clocks Input depends on Link Type and Data Type
Instance Configurable when using advanced constructors
Port Configuration Configurable when using advanced constructors

Defining Endpoints

DLsc v1 FPGA.lvlib:Endpoint.lvclass defines an endpoint.

You can find the available functions on the DLsc palette.
  • Protocol Specific Constructor—Each supported protocol defines its own set of Create Resources VIs, which defines all required inputs and returns an Endpoint object for use with the rest of the API functions. Refer to Supported Protocols for information.
  • Process—Instantiates processing logic—data buffering and protocol-specific formatting—required by the endpoint. You must place this VI on the block diagram outside of any structures. Every endpoint must call this VI.
  • Read Data Stream—Provides a 4-wire-compatible read interface for the defined endpoint. You must configure the endpoint as a Duplex Endpoint or a Read Only Endpoint for this function to compile correctly. This function is polymorphic; configure this function to match the data type and samples per cycle that were specified in the constructor.
    Note When a coprocessor is connected to a VST and the endpoint on the coprocessor sets the Ready for Output terminal to FALSE, the VST reports an overflow. This overflow condition occurs because the data on the VST is sampled continuously and can not be stopped.
  • Read Data Stream with Decimator—Provides a 4-wire-compatible read interface with the ability to set a decimation value for the defined endpoint. The built-in decimator requires a second clock that runs at two times the frequency of the clock that this method is used in. For example, if you place this method in a SCTL that uses a 160 MHz clock, you must provide a 320 MHz clock to the Clock X 2 control. You must configure the endpoint as a Duplex Endpoint or a Read Only Endpoint for this function to compile correctly. This function is polymorphic; configure this function to match the data type and samples per cycle that were specified in the constructor.
    Note When a coprocessor is connected to a VST and the endpoint on the coprocessor sets the Ready for Output terminal to FALSE, the VST reports an overflow. This overflow condition occurs because the data on the VST is sampled continuously and can not be stopped.
  • Write Data Stream—Provides a 4-wire-compatible write interface for the defined endpoint. You must configure the endpoint as a Duplex Endpoint or a Transmit Only Endpoint for this to function to compile correctly. This function is polymorphic; configure this function to match the data type and samples per cycle that were specified in the constructor.
  • Supported Protocols

    The Aurora 64B/66B is a high-speed serial protocol developed by Xilinx. DLsc Aurora 64b66b v1 FPGA.lvlib defines the protocol. You can find the available functions on the DLsc palette.

  • Create Resources Aurora 64b66b—Provides the available options for creating an endpoint that implements the Aurora 64B/66B protocol.
    • Supports creating a Transmit Only, Receive Only, or Duplex Endpoint.
    • For each direction created, you must specify the requested data type and the clock for the buffer.
      • The buffer is only used when the requested data type is less than the full width of the protocol transfer width.
      • The buffer clock frequency should be greater than or equal to the clock frequency the endpoint uses depending on the desired throughput.
    • If multiple endpoints are required on the FlexRIO coprocessor, you must use advanced constructors.
    • The constructor assumes configuration parameters for the resource based on the target and userdata width being used.
      Table 2. Standard Configuration Support
      Coprocessor VST Coprocessor CLIP Use This VI
      PXIe-6594 PXIe-5840/5841 dmsc_6594_00 Yes
      PXIe-7903 PXIe-5840/5841 dmsc_7903_00 No
      PXIe-7903 PXIe-5842 VST (Up to 2 GHz Bandwidth)

      PXIe-5842 VST with 54 GHz Frequency Extension

      dmsc_7903_01 Yes
      PXIe-7903 PXIe-5842 VST (4 GHz Bandwidth) dmsc_7903_05 Yes
      PXIe-7915 PXIe-5840/5841 dmsc_7915_00 Yes
  • Create Resources Aurora 64b66b Advanced—Provides the same options defined in the standard Create Resources 64b66b function, as well as Instance and Aurora Port Identifier. Use this function when you need to define multiple endpoints or a specific port configuration.
    • Supports creating a Transmit Only, Receive Only, or Duplex endpoint.
    • For each direction created, you must specify the requested data type and the clock for the buffer.
      • The buffer is only used when the requested data type is less than the full width of the protocol transfer width.
      • The buffer clock frequency should be greater than or equal to the clock frequency the endpoint uses depending on the desired throughput.
    • Use the Instance control to define the specific address space on the register bus. The address space is used on the host when configuration of the specific endpoint is needed.
      • In the standard Create Resources 64b66b function, the default value is 0.
      • Each endpoint in a collection must have a unique instance.
    • Use the Aurora Port Identifier control to define the specific port or combination of ports to be used. You must define the port(s) in the socketed CLIP for the FPGA Target in your project. All options are not supported on all FPGA targets.
      Note Refer to the included CLIP ReadMe.md for the port configurations in the Aurora Port Identifier, Ref Clk Frequency, and Line Rate controls. You can find ReadMe.md installed with the CLIP in the following location: <Program Files>\National Instruments\Shared\FPGA\CLIP\<Device>\<CLIP>\ReadMe.md
    • Use the Ref Clk Frequency control to define the reference clock associated with the endpoint. This value should match the selected port configuration of the CLIP that is assigned to the socketed CLIP for the FPGA target in your project.
    • Use the Line Rate control to define the line rate for the Multigigabit Transceivers (MGTs) associated with the endpoint. This value should match the selected port configuration of the CLIP that is assigned to the socketed CLIP for the FPGA target in your project.
  • Supported Data Types

  • U32—Defines an I/Q sample with the low-order 16-bit word representing I and the high-order 16-bit word representing Q. The 16-bit word represents a fixed-point data type of <±,16,1>.
  • Supported Samples per Cycle (SPC)—1, 2, 4, 8, 16, 32
    Note Some configurations do not support all samples per cycle rates.
  • Defining Endpoint Collections

    DLsc v1 FPGA.lvlib:Endpoint Collection.lvclass defines an endpoint collection.

    You must add endpoints to an endpoint collection.

    You can find the available functions on the DLsc palette.

  • Create Resources—Creates a new Endpoint Collection with all the necessary resources.
  • Add Endpoint Address Space Collection—Adds an Endpoint to the Collection. You must use this method to add all endpoints on a target to the collection.
  • Read FIFO Register Bus—Returns the FIFO register bus that is used in the Instruction Framework Host Interface.
  • Read Register Bus Clock—Returns the register bus clock that is used by the Instruction Framework Host Interface Single Cycle Time Loop.
  • Process—Creates the required processing logic for the collection. This method is required.
  • Add Subsystem—Provides a subsystem write interface to the Instruction Framework Collection Builder. This advanced function is only required when integrating other IP that uses the Instruction Framework.
  • Read Collection Builder—Returns the Instruction Framework Collection Builder from the collection. This advanced function is only required when integrating other IP that uses the Instruction Framework.
  • Write Collection Builder—Writes an Instruction Framework Collection Builder to the collection. This advanced function is only required when integrating other IP that uses the Instruction Framework.