NI Data Link System Component FPGA API
- 업데이트 날짜:2025-10-07
- 6분 (읽기 시간)
NI Data Link System Component FPGA API
The DLsc FPGA API is designed to be used in the LabVIEW FPGA environment.
The DLsc FPGA API enables creation of endpoints. Endpoints provide read and write access to target-specific CLIPs. The CLIPs define streaming protocols using the device MGTs (multi-gigabit transceivers). You can connect to devices with compatible endpoints using the defined ports on the instrument front panel. Refer to Connecting the Hardware for supported connections.
The following diagram displays the following:
- The connections of the endpoint
- The connections of the endpoint collection functions
- Outlines the decisions made during FPGA code generation
- How the data flow changes based on the user inputs
| Link Direction | Polymorphic Selector (TX, RX, DX) |
| Link Type | Constructor Type (Aurora 64B/66B) |
| Data Type | Polymorphic Selector (32 bits (16i,16q) at 1, 2, 4, 8, 16, 32 SPC) |
| Buffer Process Clocks | Input depends on Link Type and Data Type |
| Instance | Configurable when using advanced constructors |
| Port Configuration | Configurable when using advanced constructors |
Defining Endpoints
DLsc v1 FPGA.lvlib:Endpoint.lvclass defines an endpoint.
Supported Protocols
The Aurora 64B/66B is a high-speed serial protocol developed by Xilinx. DLsc Aurora 64b66b v1 FPGA.lvlib defines the protocol. You can find the available functions on the DLsc palette.
- Supports creating a Transmit Only, Receive Only, or Duplex Endpoint.
- For each direction created, you must specify the requested data type
and the clock for the buffer.
- The buffer is only used when the requested data type is less than the full width of the protocol transfer width.
- The buffer clock frequency should be greater than or equal to the clock frequency the endpoint uses depending on the desired throughput.
- If multiple endpoints are required on the FlexRIO coprocessor, you must use advanced constructors.
- The constructor assumes configuration parameters for the resource
based on the target and userdata width being used.
Table 2. Standard Configuration Support Coprocessor VST Coprocessor CLIP Use This VI PXIe-6594 PXIe-5840/5841 dmsc_6594_00 Yes PXIe-7903 PXIe-5840/5841 dmsc_7903_00 No PXIe-7903 PXIe-5842 VST (Up to 2 GHz Bandwidth) PXIe-5842 VST with 54 GHz Frequency Extension
dmsc_7903_01 Yes PXIe-7903 PXIe-5842 VST (4 GHz Bandwidth) dmsc_7903_05 Yes PXIe-7915 PXIe-5840/5841 dmsc_7915_00 Yes
- Supports creating a Transmit Only, Receive Only, or Duplex endpoint.
- For each direction created, you must specify the requested data type
and the clock for the buffer.
- The buffer is only used when the requested data type is less than the full width of the protocol transfer width.
- The buffer clock frequency should be greater than or equal to the clock frequency the endpoint uses depending on the desired throughput.
- Use the Instance control to define the
specific address space on the register bus. The address space is
used on the host when configuration of the specific endpoint is
needed.
- In the standard Create Resources 64b66b function, the default value is 0.
- Each endpoint in a collection must have a unique instance.
- Use the Aurora Port Identifier control to
define the specific port or combination of ports to be used. You
must define the port(s) in the socketed CLIP for the FPGA Target in
your project. All options are not supported on all FPGA
targets.Note Refer to the included CLIP ReadMe.md for the port configurations in the Aurora Port Identifier, Ref Clk Frequency, and Line Rate controls. You can find ReadMe.md installed with the CLIP in the following location: <Program Files>\National Instruments\Shared\FPGA\CLIP\<Device>\<CLIP>\ReadMe.md
- Use the Ref Clk Frequency control to define the reference clock associated with the endpoint. This value should match the selected port configuration of the CLIP that is assigned to the socketed CLIP for the FPGA target in your project.
- Use the Line Rate control to define the line rate for the Multigigabit Transceivers (MGTs) associated with the endpoint. This value should match the selected port configuration of the CLIP that is assigned to the socketed CLIP for the FPGA target in your project.
Supported Data Types
Defining Endpoint Collections
DLsc v1 FPGA.lvlib:Endpoint Collection.lvclass defines an endpoint collection.
You must add endpoints to an endpoint collection.
You can find the available functions on the DLsc palette.
관련 콘텐츠
- Connecting the Hardware
Cable the VST to the coprocessor.