NIHSDIO_ATTR_DATA_POSITION_DELAY

Specific Attribute

Description

Specifies the delay after the Sample clock rising edge when the device generates or acquires a new data sample. Data delay is expressed as a fraction of the clock period (for example, a fraction of 1/NIHSDIO_ATTR_SAMPLE_CLOCK_RATE). This attribute is relevant only when the NIHSDIO_ATTR_DATA_POSITION attribute is set to NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE.

Note  On NI 6555/6556 devices, valid values range from –1 to 2 clock cycles in increments of 0.001 cycles. Delay on NI 6555/6556 devices is configured on a per channel basis.

Note  To configure a delay on NI 656x devices, you must delay all channels on the device. NI-HSDIO returns an error if you apply a delay to only a partial channel list.

The NI 6547/6548 supports multibank data delay. All channels configured to NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE and assigned to the same data delay bank must share a data delay value, even if channels on that bank are configured to NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE or NIHSDIO_VAL_SAMPLE_CLOCK_FALLING_EDGE. NI-HSDIO returns an error if you set different delay values for two channels within the same bank.

The following table shows which channels belong to each bank.

Note  DDR and extended data states do not change the bank assignments.

Related topics:

• Data Position Delay Resolution