NIHSDIO_ATTR_DATA_POSITION
- Updated2023-02-21
- 2 minute(s) read
Specific Attribute
| Data type |
Access | Applies to | Coercion | High-Level Functions |
|---|---|---|---|---|
| ViInt32 | R/W | Channel | None | niHSDIO_ConfigureDataPosition |
Description
Specifies the data position for the operation, which specifies which edge of the Sample clock is used to time the generation or acquisition. You can also configure the device to generate or acquire data at a configurable delay past each rising edge of the Sample clock. When this attribute is set to NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE, use the NIHSDIO_ATTR_DATA_POSITION_DELAY attribute to specify the delay value. This attribute is relevant only when the NIHSDIO_ATTR_DATA_POSITION attribute is set to NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE. Refer to the Alphabetical Attributes List topic for a list of default values per device.
This attribute applies to static and dynamic data operations.
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Note On NI 6555/6556 devices, this attribute is per channel selectable. |
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Note To configure a delay on NI 656x devices, you must delay all channels on the device. NI-HSDIO returns an error if you apply a delay to only a partial channel list. |
Refer to the NIHSDIO_ATTR_DATA_POSITION_DELAY attribute for more information about multibank data delay.
Defined Values:
| NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE (18) | Samples or generates data on the Sample clock rising edge. |
| NIHSDIO_VAL_SAMPLE_CLOCK_FALLING_EDGE (19) | Samples or generates data on the Sample clock falling edge. |
| NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE (20) | Samples or generates data with a delay from the Sample clock rising edge. Specify the delay using the NIHSDIO_ATTR_DATA_POSITION_DELAY attribute. This value has more jitter than the rising or falling edge values. Certain devices have Sample clock frequency limitations on when a custom delay can be used. Refer to the device sections for details. |