Delays input value for a number of loop iterations. This VI is analogous to a z^-n block where n can be constant or variable.

This function supports scalar and array values of integer, fixed-point, and Boolean data types, clusters, and arrays of clusters.


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Dialog Box Options

Parameter Description
General

Specifies general information about this function.

  • Data Type—Contains information about the data type of the D input terminal.
    • Width—Specifies the number of bits of D, which affects the number of internal registers this function creates.
      If you wire an integer or a fixed-point data type to D, LabVIEW dims this option and sets it to the word length of the data type you wire. If you wire a Boolean, cluster, or fixed-size array, LabVIEW dims this option and sets D to the combined word length of all elements in the data type.
      Note The data type of D does not adapt to source.
  • Optional Terminal—Contains information about an optional input terminal.
    • Enable—Specifies whether LabVIEW displays the enable input terminal. By default, this checkbox does not contain a checkmark and LabVIEW sets the value of this terminal to TRUE.
  • Delay Settings—Contains options relating to the delay.
    • Constant delay—Specifies that this function applies a constant delay
      • Delay—Specifies the number of clock cycles by which this function delays D. Delay must be less than or equal to 512 cycles. The default value is 1 cycle.
    • Dynamic delay—Specifies that this function applies a variable delay.
      • Maximum delay—Specifies the maximum number of clock cycles by which this function can delay D, which in turn specifies the number of internal registers this function uses. The value must be between 16 and 512 cycles, inclusive. Use the n–1 input terminal to specify which register reaches the output terminal Q.
  • Resulting schematic—Displays the FPGA logic of this function. The schematic changes based on the configuration options you select.
Initial Values Contains settings for the initial values of the internal registers this function uses.
  • Initialization—Specifies when and how the internal registers reset or initialize.
    • Reset to zeros on first call—Specifies that when you first call this function or invoke the Reset method, all internal registers reset to 0.
    • Initialize on compile or load—Specifies that when you compile or load the VI that contains this function, internal registers initialize to the values you define in the Initial Values table. This function does nothing if the FPGA is reset using the Reset method.
  • Initialization VI—Contains options about the initialization VI LabVIEW uses to initialize the internal registers of this function. These options are available only if you select the Initialize on compile or load option in the Initialization section.
    • VI Path—Specifies the path to the VI that provides initial values to this function.
    • New VI from Template—Creates an instance of a template VI and opens the VI. You can use this template to create an initialization VI. You must close this configuration dialog box to edit the VI.
    • Open VI—Opens the VI you specify in the VI Path field. You must close this dialog box to edit the VI.
    • Run VI—Runs the VI you specify in the VI Path field and populates the Initial Values table with the values the VI returns.

      If the output data type of the initialization VI is different from the data type of the Discrete Delay function, LabVIEW attempts to coerce the output values to the data type of the function. If this coercion does not succeed, LabVIEW displays an error message.

  • Initial Values—Specifies the initial values of this function in hexadecimal, decimal, or binary format. This table is available only if you select the Initialize on compile or load option in the Initialization section.

    If you wire a cluster or a non-Boolean fixed-size array to the D input terminal, you cannot use this table to specify initial values. Instead, you must either select the Reset to zeros on first call option or use the Initialization VI section to define custom initial values.
Configuration Feedback

Displays information about how this function executes. This information is based on the configuration options you specify.

Inputs/Outputs

  • cbool.png D —

    Specifies the data to delay.

    Note The data type of D does not adapt to source.
  • n-1 —

    Specifies the index of the internal register whose value reaches the Q output terminal. The value of n–1 can be between 0 and n–1, where n is the value of the Maximum delay control in the configuration dialog box.

    LabVIEW displays this terminal only if you select the Dynamic delay option in the configuration dialog box.

  • enable —

    Specifies whether this function ignores the input terminal D. The default value is TRUE, which means this function shifts all values to the next internal register and takes in a value of D to the first internal register. If enable is FALSE, this function ignores D and does not shift existing values, which means the internal registers retain the value they had during the previous clock cycle.

    Use this terminal to operate on only valid values of D. For example, you can wire the output valid output terminal of a High Throughput Math function to this input terminal. In this situation, the Discrete Delay function takes in a value of D only if the incoming value is valid.

    LabVIEW displays enable only if you place a checkmark in the Enable checkbox in the configuration dialog box. If you do not display this terminal, LabVIEW sets it to TRUE internally.

  • ibool.png Q —

    Returns the delayed value of D. If this function is set to Constant delay, Q returns the value of the last internal register. If this function is set to Dynamic delay, Q returns the value of the register you specify with the n–1 input terminal.

    • This function implements delays by using shift register lookup tables (SRLs) instead of flip-flops. SRLs combine many delays into a single lookup table (LUT), which can reduce FPGA resource usage significantly compared to flip-flops.

    Differences between the Discrete Delay Function and the Feedback Node

    The Feedback Node and the Discrete Delay function are similar but have some key differences. The following table provides information about the differences between these objects.

    Feedback Node Discrete Delay Function Recommendation
    Design and Features
    • Designed for feeding back output signals to an input.
    • Designed for delaying an input signal by a constant number of clock cycles.
    		 Designed for delaying an input signal by a constant or variable number of clock cycles. Use the function that represents the use case you are programming.
    Initialization options
    • Initialize internal registers to custom values on first call to the FPGA VI or when the FPGA VI resets
    • Initialize internal registers to custom values when the FPGA VI compiles or loads or when the FPGA VI resets
    • Initialize internal registers to custom values when the FPGA VI compiles or loads, ignoring an FPGA VI resets
    • Reset internal registers to zeroes on the first call to the FPGA VI or when the FPGA VI resets
    • Initialize internal registers to custom values when the FPGA VI compiles or loads, ignoring an FPGA VI resets
    		 The Discrete Delay implements delays by using SRLs instead of flip-flops. SRLs combine many delays into a single lookup table (LUT), which can reduce FPGA resource usage significantly compared to flip-flops.
    Ways of defining initial values You define initial values by wiring a value to the initializer terminal on the diagram. You define initial values by using the Initial Values table or by using a custom initialization VI. Use the Discrete Delay function if you have an initialization VI or if you need to delay a fixed-size array.
    Support for dynamic delay Use the Discrete Delay function if you need a dynamic delay.
    Support for representing feedback on a block diagram Use the Feedback Node if you need to represent feedback on a block diagram.

    Constant Delay vs. Dynamic Delay

    The following example illustrates the differences between a Constant delay and a Dynamic delay.

    If you set Constant delay to 20 clock cycles, this function creates 20 internal registers, numbered 0 through 19, to store values you wire to D. A value you send to D on the first clock cycle will be stored until the 20th clock cycle, assuming the value of the enable terminal is TRUE.

    As you send new values to D, the function shifts values from one register to another. The original value you enter moves from register 0, to register 1, to register 2, and so on, until the value reaches register 19 on the 20th clock cycle. On the 21st clock cycle, the output terminal Q returns the value you entered during the first clock cycle. The value has been delayed for 20 clock cycles.

    The function behaves similarly for a Dynamic delay. If you set Maximum delay to 20 clock cycles, the function also creates 20 registers for storing values. A value you wire to D moves from register 0 to register 19 with each successive clock cycle.

    However, the function also displays the n–1 input terminal, which you use to specify the number of an internal register. Q returns the value of this register instead of always returning the value of the last register.

    For example, if 17 clock cycles have elapsed, the value of D you sent during the first clock cycle is in register 16. If you wire a value of 16 to n–1 during the 18th clock cycle, the function returns this value. The value has been delayed for 17 clock cycles, not 20.

    Simulation Export Details

    This node can increase simulation run time significantly when used in conjunction with downloading, stopping, or running the FPGA VI.

    Examples

    Refer to the following example files included with LabVIEW FPGA Module.

    • labview\examples\CompactRIO\FPGA Fundamentals\FPGA Math and Analysis\High-Throughput Math\Multi-Channel Averaging\Multi-Channel Averaging.lvproj
    • labview\examples\R Series\FPGA Fundamentals\FPGA Math and Analysis\High-Throughput Math\Multi-Channel Averaging\Multi-Channel Averaging.lvproj