Retrieves data you request with the Request Data method.

Use the Memory Method Node to implement this method. Only DRAM memory supports this method.

Inputs/Outputs

Option Description
Memory In Specifies the FPGA memory. If you leave Memory In unwired, you can specify the FPGA memory by right-clicking the Memory Method Node and selecting a memory item from the shortcut menu. Otherwise, you can wire a Memory control, Memory constant, or another Memory Method node to Memory In.
Ready for Output Specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
Note If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
Memory Out Returns Memory In if Memory In is wired. Otherwise, Memory Out returns the memory that you specify in the Memory Method Node.
Data Is the data retrieved from memory on the FPGA target. Data is directly accessible only from within the FPGA VI. You cannot directly access the data in the memory of the FPGA target from the host VI. You must use controls, indicators, or DMA FIFOs to access data from the host VI.

The Data data type is the data type you configure in the Memory Properties dialog box when you create the memory item. If you do not initialize the memory item, the data is undefined.
Output Valid Returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

This method retrieves data in the same order that the Request Data method requests it.

Note The Write (Memory Method) node can be placed in a different clock domain than the corresponding Request Data and Retrieve Data nodes.

Considerations for Single-Cycle Timed Loops

You can use this method only inside a single-cycle Timed Loop.