VirtualBench User Manual

What Is a Pattern Trigger?

  • Updated2023-09-07
  • 2 minute(s) read

What Is a Pattern Trigger?

A pattern trigger acts like a combination lock. When you enter the correct combination, the lock opens. In the case of triggers, when the device matches the desired pattern, the pattern trigger is asserted. A pattern trigger allows you to configure the device to monitor the logic analyzer inputs for a specific pattern. When the device acquires this pattern, the device asserts the pattern trigger.

The pattern trigger source for the oscilloscope can be any of the following signals:

  • 34 logic analyzer inputs
  • Eight digital I/O lines
  • External trigger through the TRIG BNC
  • 60 Hz/50 Hz AC line
  • FGEN Start

The digital pattern is specified using the following characters:

  • X: ignore the channel
  • 0: Match on a logic low level on the channel
  • 1: Match on a logic high level on the channel
  • R: Match on rising edge on the channel
  • E: Match on either rising or falling edge on the channel
  • F: Match on falling edge on the channel

To meet the trigger condition, the combination of specified trigger conditions must be met as follows:

  • The level trigger conditions specified in a pattern (0 and 1) are logically ANDed together.
  • The edge trigger conditions specified in a pattern (R, E, and F) are logically ORed together.
  • The result of both of those operations are then logically ANDed together.

Example

For example, if you specify a pattern of "RFX11100" for D7-D0, that pattern specifies these conditions:

Channel Pattern
Character
Description
D7 R Match on rising edge on the channel
D6 F Match on falling edge on the channel
D5 X Ignore the channel
D4 1 Match on a logic high level on the channel
D3 1 Match on a logic high level on the channel
D2 1 Match on a logic high level on the channel
D1 0 Match on a logic low level on the channel
D0 0 Match on a logic low level on the channel

A pattern match occurs when channels D4, D3, D2 are logic high, AND lines D1, D0 are logic low, while D7 has a rising edge, OR D6 has a falling edge. D5 is ignored.

The Boolean logic is shown in the following illustration.

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