Using the Ettus USRP X410 with the LabVIEW FPGA Module

Complete the following steps to route a signal into or out of the LabVIEW FPGA Module using the TRIG IN/OUT port on the Ettus USRP X410 device. This allows you to provide an external trigger signal for synchronous triggering of your application.

  1. Verify that you have downloaded compatible versions of NI-USRP and LabVIEW FPGA. Check your product Readme for details.
  2. Optionally, change the behavior of the FPGA image.
    1. Open the Reference FPGA Project from <LabVIEW directory> » instr.lib » niUSRP » Reference FPGA.
    2. In the Reference FPGA Project, the Trig Out Routing VI shows the default behavior, which is to route PPS IN to TRIG OUT. A TRIG IN object can also be added from the Project Explorer window. To change the default behavior, TRIG IN and TRIG OUT can be routed to VIs that you add to the project from the FPGA I/O palette
    3. Compile the FPGA.
  3. Specify the desired interaction between the physical Trig Input/Output port and objects in LabVIEW FPGA.
    1. Adjust the Trig I/O Mode property within the niUSRP Property Node VI. The options for the property are Input, Output, and Off.
      Table 7. niUSRP Property Node VI Properties
      Property Description
      Off By default, the property is set to Off. In this state, the TRIG IN/OUT port is not in use.
      Input When the property is set to Input, the signal that is going into the TRIG IN/OUT port on the device is routed to the TRIG IN object in LabVIEW FPGA.
      Output When the property is set to Output, the signal from the TRIG OUT object in LabVIEW FPGA is routed to the TRIG IN/OUT port on the device.
    2. For applications where the Trig I/O Mode property in the niUSRP Property Node VI is set to Input or Output, ensure that an SMA (m)-to-SMA (m) cable connects the appropriate hardware to the TRIG IN/OUT port on your device.